PI7C8150BMA-33 datasheet(94/107 Pages) PERICOM

94 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 94 of 107

April 2015 – Revision 2.1

BRIDGE BEHAVIOR

A PCI cycle is initiated by asserting the FRAME_L signal. In a bridge, there are a number

of possibilities. Those possibilities are summarized in the table below:

15.1

BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES

Initiator

Target

Response

Master on Primary

Target on Primary

PI7C8150B does not respond. It detects

this situation by decoding the address as

well as monitoring the P_DEVSEL_L for

other fast and medium devices on the

Primary Port.

Master on Primary

Target on Secondary

PI7C8150B asserts P_DEVSEL_L,

terminates the cycle normally if it is able

to be posted, otherwise return with a retry.

It then passes the cycle to the appropriate

port. When the cycle is complete on the

target port, it will wait for the initiator to

repeat the same cycle and end with normal

termination.

Master on Primary

Target not on Primary nor

Secondary Port

PI7C8150B does not respond and the

cycle will terminate as master abort.

Master on Secondary

Target on the same

Secondary Port

PI7C8150B does not respond.

Master on Secondary

Target on Primary or the

other Secondary Port

PI7C8150B asserts S_DEVSEL_L,

terminates the cycle normally if it is able

to be posted, otherwise returns with a

retry. It then passes the cycle to the

appropriate port. When cycle is complete

on the target port, it will wait for the

initiator to repeat the same cycle and end

with normal termination.

Master on Secondary

Target not on Primary nor

the other Secondary Port

PI7C8150B does not respond.

15.2

ABNORMAL TERMINATION (INITIATED BY BRIDGE

MASTER)

15.2.1

MASTER ABORT

Master abort indicates that when PI7C8150B acts as a master and receives no response (i.e.,

no target asserts DEVSEL_L or S_DEVSEL_L) from a target, the bridge de-asserts

FRAME_L and then de-asserts IRDY_L.

15.2.2

PARITY AND ERROR REPORTING

Parity must be checked for all addresses and write data. Parity is defined on the P_PAR,

and S_PAR signals. Parity should be even (i. e. an even number of‘1’s) across AD, CBE,

and PAR. Parity information on PAR is valid the cycle after AD and CBE are valid. For

reads, even parity must be generated using the initiators CBE signals combined with the

15-0048

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