PI7C8150BMA-33 datasheet(6/107 Pages) PERICOM

6 / 107 page

PI7C8150B

ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE

Page 6 of 107

April 2015 – Revision 2.1

4.3.2

PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS ..................44

4.4

VGA SUPPORT ............................................................................................................................45

4.4.1

VGA MODE ..........................................................................................................................46

4.4.2

VGA SNOOP MODE............................................................................................................46

TRANSACTION ORDERING...........................................................................................................46

5.1

TRANSACTIONS GOVERNED BY ORDERING RULES .........................................................47

5.2

GENERAL ORDERING GUIDELINES.......................................................................................47

5.3

ORDERING RULES .....................................................................................................................48

5.4

DATA SYNCHRONIZATION .....................................................................................................49

ERROR HANDLING..........................................................................................................................50

6.1

ADDRESS PARITY ERRORS......................................................................................................50

6.2

DATA PARITY ERRORS.............................................................................................................51

6.2.1

CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE ...........51

6.2.2

READ TRANSACTIONS .....................................................................................................51

6.2.3

DELAYED WRITE TRANSACTIONS................................................................................52

6.2.4

POSTED WRITE TRANSACTIONS ...................................................................................54

6.3

DATA PARITY ERROR REPORTING SUMMARY ..................................................................56

6.4

SYSTEM ERROR (SERR_L) REPORTING ................................................................................59

EXCLUSIVE ACCESS .......................................................................................................................60

7.1

CONCURRENT LOCKS ..............................................................................................................60

7.2

ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8150B ......................................................60

7.2.1

LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION ......................................61

7.2.2

LOCKED TRANSACTION IN UPSTREAM DIRECTION ...............................................62

7.3

ENDING EXCLUSIVE ACCESS .................................................................................................62

PCI BUS ARBITRATION ..................................................................................................................63

8.1

PRIMARY PCI BUS ARBITRATION..........................................................................................63

8.2

SECONDARY PCI BUS ARBITRATION....................................................................................64

8.2.1

SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER .....................64

8.2.2

PREEMPTION .....................................................................................................................65

8.2.3

SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER.......................65

8.2.4

BUS PARKING.....................................................................................................................65

CLOCKS ..............................................................................................................................................66

9.1

PRIMARY CLOCK INPUTS ........................................................................................................66

9.2

SECONDARY CLOCK OUTPUTS..............................................................................................66

9.3

ASYNCHRONOUS MODE ..........................................................................................................66

GENERAL PURPOSE I/O INTERFACE.....................................................................................67

10.1

GPIO CONTROL REGISTERS ....................................................................................................67

10.2

SECONDARY CLOCK CONTROL .............................................................................................68

10.3

LIVE INSERTION ........................................................................................................................69

PCI POWER MANAGEMENT .....................................................................................................70

RESET ..............................................................................................................................................71

12.1

PRIMARY INTERFACE RESET .................................................................................................71

12.2

SECONDARY INTERFACE RESET ...........................................................................................71

12.3

CHIP RESET .................................................................................................................................71

SUPPORTED COMMANDS..........................................................................................................72

13.1

PRIMARY INTERFACE ..............................................................................................................72

15-0048

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