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ATtiny167-ESSZ датащи(PDF) 209 Page - ATMEL Corporation |
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ATtiny167-ESSZ датащи(HTML) 209 Page - ATMEL Corporation |
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209 / 282 page ![]() 209 7728D–AVR–07/09 ATtiny87/ATtiny167 17.11.4 ADCSRB – ADC Control and Status Register B • Bit 7– BIN: Bipolar Input Mode The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions are supported and the voltage on the positive input must always be larger than the voltage on the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode two-sided conversions are supported and the result is represented in the two’s complement form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits + 1 sign bit. • Bit 3 – Res: Reserved Bit This bit is reserved for future use. For compatibility with future devices it must be written to zero when ADCSRB register is written. • Bits 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA register is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA register is set, this will start a conver- sion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. 17.11.5 DIDR0 – Digital Input Disable Register 0 Bit 7 65 43210 BIN ACME ACIR1 ACIR0 – ADTS2 ADTS1 ADTS0 ADCSRB Read/Write R/W R/W R/W R/W R R/W R/W R/W Initial Value 0 00 00000 Table 17-7. ADC Auto Trigger Source Selections ADTS2 ADTS1 ADTS0 Trigger Source 0 0 0 Free Running mode 0 0 1 Analog Comparator 0 1 0 External Interrupt Request 0 0 1 1 Timer/Counter1 Compare Match A 1 0 0 Timer/Counter1 Overflow 1 0 1 Timer/Counter1 Compare Match B 1 1 0 Timer/Counter1 Capture Event 1 1 1 Watchdog Interrupt Request Bit 7 6 543210 ADC7D / AIN1D ADC6D / AIN0D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 000000 |
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