ATtiny167-ESSZ datasheet(210/282 Pages) ATMEL

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7728D–AVR–07/09

ATtiny87/ATtiny167

• Bits 7:0 – ADC7D:ADC0D: ADC7:0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN register bit will always read as zero when this bit is set. When

an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed,

this bit should be written logic one to reduce power consumption in the digital input buffer.

17.11.6

DIDR1 – Digital Input Disable Register 1

• Bit 7 – Res: Reserved Bit

This bit is reserved for future use. For compatibility with future devices it must be written to

zero when DIDR1 register is written.

• Bits 6..4 – ADC10D..ADC8D: ADC10..8 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN register bit will always read as zero when this bit is set. When

an analog signal is applied to the ADC10:8 pin and the digital input from this pin is not needed,

this bit should be written logic one to reduce power consumption in the digital input buffer.

• Bits 3:0 - Reserved Bits

These bits are reserved for future use. For compatibility with future devices, they must be writ-

ten to zero when DIDR1 is written.

17.11.7

AMISCR – Analog Miscellaneous Control Register

• Bits 7:3 – Reserved Bits

These bits are reserved for future use. For compatibility with future devices, they must be writ-

ten to zero when AMISCR is written.

• Bit 2 – AREFEN: External Voltage Reference Input Enable

When this bit is written logic one, the voltage reference for the ADC is input from AREF pin as

described in Table 17.10 on page 204. If active channels are used, using AVcc or an external

AREF higher than (AVcc - 1V) is not recommended, as this will affect ADC accuracy. The

internal voltage reference options may not be used if an external voltage is being applied to

the AREF pin. It is recommended to use DIDR register bit function (digital input disable) when

AREFEN is set.

• Bit 1 – XREFEN: Internal Voltage Reference Output Enable

When this bit is written logic one, the internal voltage reference 1.1V or 2.56V is output on

XREF pin as described in Table 17.10 on page 204. It is recommended to use DIDR register

bit function (digital input disable) when XREFEN is set.

Bit

765

4321

ADC10D

ADC9D

ADC8D

DIDR1

Read/Write

R/W

RRRR

Initial Value

000

0000

Bit

5432

---

AREFEN

XREFEN

ISRCEN

AMISCR

Read/Write

RRRR

R/W

Initial Value

0000

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