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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny167-ESSZ датащи(PDF) 182 Page - ATMEL Corporation |
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ATtiny167-ESSZ датащи(HTML) 182 Page - ATMEL Corporation |
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182 / 282 page  182 7728D–AVR–07/09 ATtiny87/ATtiny167 15.6.2 LIN Status and Interrupt Register - LINSIR • Bits 7:5 - LIDST[2:0]: Identifier Status – 0xx = no specific identifier, – 100 = Identifier 60 (0x3C), – 101 = Identifier 61 (0x3D), – 110 = Identifier 62 (0x3E), – 111 = Identifier 63 (0x3F). • Bit 4 - LBUSY: Busy Signal – 0 = Not busy, – 1 = Busy (receiving or transmitting). • Bit 3 - LERR: Error Interrupt It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective enable bit - LENERR - is set in LINENIR. –0 = No error, – 1 = An error has occurred. The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also resets all LINERR bits. In UART mode, this bit is also cleared by reading LINDAT. • Bit 2 - LIDOK: Identifier Interrupt This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR. – 0 = No identifier, – 1 = Slave task: Identifier present, master task: Tx Header complete. The user clears this bit by writing 1, in order to reset this interrupt. • Bit 1 - LTXOK: Transmit Performed Interrupt This bit generates an interrupt if its respective enable bit - LENTXOK - is set in LINENIR. –0 = No Tx, –1 = Tx Response complete. The user clears this bit by writing 1, in order to reset this interrupt. In UART mode, this bit is also cleared by writing LINDAT. Bit 76543210 LIDST2 LIDST1 LIDST0 LBUSY LERR LIDOK LTXOK LRXOK LINSIR Read/Write RRRR R/Wone R/Wone R/Wone R/Wone Initial Value 00000000 |
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