ATtiny167-ESSZ datasheet(179/282 Pages) ATMEL

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179

7728D–AVR–07/09

ATtiny87/ATtiny167

The LIN protocol says that a message with an identifier from 60 (0x3C) up to 63 (0x3F) uses a

classic checksum (sum over the data bytes only). Software will be responsible for switching

correctly the LIN13 bit to provide/check this expected checksum (the insertion of the ID field in

the computation of the CRC is set - or not - just after entering the Rx or Tx Response

command).

15.5.15

Data Management

15.5.15.1

LIN FIFO Data Buffer

To preserve register allocation, the LIN data buffer is seen as a FIFO (with address pointer

accessible). This FIFO is accessed via the LINDX[2..0] field of LINSEL register through the

LINDAT register.

LINDX[2..0], the data index, is the address pointer to the required data byte. The data byte can

be read or written. The data index is automatically incremented after each LINDAT access if

the LAINC (active low) bit is cleared. A roll-over is implemented, after data index=7 it is data

index=0. Otherwise, if LAINC bit is set, the data index needs to be written (updated) before

each LINDAT access.

The first byte of a LIN frame is stored at the data index=0, the second one at the data index=1,

and so on. Nevertheless, LINSEL must be initialized by the user before use.

15.5.15.2

UART Data Register

The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will

be for data out and in read access, LINDAT will be for data in.

In UART mode the LINSEL register is unused.

15.5.16

OCD Support

When a debugger break occurs, the state machine of the LIN/UART controller is stopped

(included frame time-out) and further communication may be corrupted.

ATtiny167-ESSZ датащи(PDF) 179 Page - ATMEL Corporation