ATtiny167-ESSZ datasheet(147/282 Pages) ATMEL

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147

7728D–AVR–07/09

ATtiny87/ATtiny167

13.2.4

SPI Status Register – SPSR

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in

SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI

is in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first read-

ing the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The

WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL

set, and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the ATtiny87/167 and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the

SPI is in Master mode (see Table 13-4). This means that the minimum SCK period will be two

CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at

clkio/4 or lower.

The SPI interface on the ATtiny87/167 is also used for program memory and EEPROM down-

loading or uploading. See “Serial Downloading” on page 238 for serial programming and

verification.

13.2.5

SPI Data Register – SPDR

• Bits 7:0 - SPD7:0: SPI Data

The SPI Data Register is a read/write register used for data transfer between the Register File

and the SPI Shift Register. Writing to the register initiates data transmission. Reading the reg-

ister causes the Shift Register Receive buffer to be read.

Bit

6543

210

SPIF

WCOL

–

SPI2X

SPSR

Read/Write

RRRR

R/W

Initial Value

0000

000

Bit

7654

3210

SPD7SPD6SPD5SPD4SPD3SPD2SPD1SPD0

SPDR

Read/Write

R/W

Initial Value

XXXXXXXX

Undefined

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