ATtiny167-ESSZ datasheet(145/282 Pages) ATMEL

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7728D–AVR–07/09

ATtiny87/ATtiny167

13.2

SS Pin Functionality

13.2.1

Slave Mode

When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is

held low, the SPI is activated, and MISO becomes an output if configured so by the user. All

other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which

means that it will not receive incoming data. Note that the SPI logic will be reset once the SS

pin is driven high.

The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous

with the master clock generator. When the SS pin is driven high, the SPI slave will immediately

reset the send and receive logic, and drop any partially received data in the Shift Register.

13.2.2

Master Mode

When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the

direction of the SS pin.

If SS is configured as an output, the pin is a general output pin which does not affect the SPI

system. Typically, the pin will be driving the SS pin of the SPI Slave.

If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS

pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin

defined as an input, the SPI system interprets this as another master selecting the SPI as a

slave and starting to send data to it. To avoid bus contention, the SPI system takes the follow-

ing actions:

The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result

of the SPI becoming a Slave, the MOSI and SCK pins become inputs.

The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in

SREG is set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a pos-

sibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If

the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI

Master mode.

13.2.3

SPI Control Register – SPCR

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if

the Global Interrupt Enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI

operations.

Bit

6543

210

SPIE

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

SPCR

Read/Write

R/W

Initial Value

0000

000

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