ATtiny167-ESSZ datasheet(146/282 Pages) ATMEL

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7728D–AVR–07/09

ATtiny87/ATtiny167

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic

zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be

cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable

SPI Master mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is

low when idle. Refer to Figure 13-3 and Figure 13-4 for an example. The CPOL functionality is

summarized below:

• Bit 2 – CPHA: Clock Phase

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first)

or trailing (last) edge of SCK. Refer to Figure 13-3 and Figure 13-4 for an example. The CPOL

functionality is summarized below:

• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0

These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0

have no effect on the Slave. The relationship between SCK and the clk

IO frequency fclkio is

shown in the following table:

Table 13-2.

CPOL Functionality

CPOL

Leading Edge

Trailing Edge

Rising

Falling

Rising

Table 13-3.

CPHA Functionality

CPHA

Leading Edge

Trailing Edge

Sample

Setup

Sample

Table 13-4.

Relationship Between SCK and the Oscillator Frequency

SPI2X

SPR1

SPR0

SCK Frequency

fclkio/4

fclkio/16

fclkio/64

fclkio/128

fclkio/2

fclkio/8

fclkio/32

fclkio/64

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