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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ATtiny167-ESSZ датащи(PDF) 132 Page - ATMEL Corporation |
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ATtiny167-ESSZ датащи(HTML) 132 Page - ATMEL Corporation |
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132 / 282 page  132 7728D–AVR–07/09 ATtiny87/ATtiny167 Figure 12-14. Timer/Counter Timing Diagram, with Prescaler (f clk_I/O/8) 12.11 16-bit Timer/Counter Register Description 12.11.1 Timer/Counter1 Control Register A – TCCR1A • Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A • Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1Ai and OC1Bi respec- tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1Ai output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1Bi output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit and OC1xi bit (TCCR1D) corresponding to the OC1Ai or OC1Bi pin must be set in order to enable the output driver. When the OC1Ai or OC1Bi is connected to the pin, the function of the COM1A/B1:0 bits is dependent of the WGM13:0 bits setting. Table 12-1 shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). TOVn(FPWM) and ICF n(if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clk I/O clk Tn (clk I/O/8) Bit 7 654 32 1 0 COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 TCCR1A Read/Write R/W R/W R/W R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 12-1. Compare Output Mode, non-PWM OC1Ai OC1Bi COM1A1 COM1B1 COM1A0 COM1B0 Description 0x x Normal port operation, OC1A/OC1B disconnected. 1 00 0 1 Toggle OC1A/OC1B on Compare Match. 10 Clear OC1A/OC1B on Compare Match (Set output to low level). 1 1 Set OC1A/OC1B on Compare Match (Set output to high level). |
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