ATtiny167-ESSZ datasheet(129/282 Pages) ATMEL

129 / 282 page

129

7728D–AVR–07/09

ATtiny87/ATtiny167

In phase and frequency correct PWM mode the counter is incremented until the counter value

matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The

counter has then reached the TOP and changes the count direction. The TCNT1 value will be

equal to TOP for one timer clock cycle. The timing diagram for the phase correct and fre-

quency correct PWM mode is shown on Figure 12-10. The figure shows phase and frequency

correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the

timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram

includes non-inverted and inverted PWM outputs. The small horizontal line marks on the

TCNT1 slopes represent compare matches between OCR1A/B and TCNT1. The OC1A/B

interrupt flag will be set when a compare match occurs.

Figure 12-10. Phase and Frequency Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1A/B

Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or

ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached

TOP. The interrupt flags can then be used to generate an interrupt each time the counter

reaches the TOP or BOTTOM value.

When changing the TOP value the program must ensure that the new TOP value is higher or

equal to the value of all of the Compare Registers. If the TOP value is lower than any of the

Compare Registers, a compare match will never occur between the TCNT1 and the

OCR1A/B.

As Figure 12-10 shows the output generated is, in contrast to the phase correct mode, sym-

metrical in all periods. Since the OCR1A/B Registers are updated at BOTTOM, the length of

the rising and the falling slopes will always be equal. This gives symmetrical output pulses and

is therefore frequency correct.

Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using

ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. How-

ever, if the base PWM frequency is actively changed by changing the TOP value, using the

OCR1A as TOP is clearly a better choice due to its double buffer feature.

OCRnx/TOP Update and

TOVn Interrupt Flag Set

(Interrupt on Bottom)

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TCNTn

Period

OCnxi

(COMnx1:0 = 2)

(COMnx1:0 = 3)

ATtiny167-ESSZ датащи(PDF) 129 Page - ATMEL Corporation

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