ATtiny167-ESSZ datasheet(130/282 Pages) ATMEL

130 / 282 page

130

7728D–AVR–07/09

ATtiny87/ATtiny167

In phase and frequency correct PWM mode, the compare units allow generation of PWM

waveforms on the OC1A/B pins. Setting the COM1A/B1:0 bits to two will produce a

non-inverted PWM and an inverted PWM output can be generated by setting the COM1A/B1:0

to three (See Table on page 133). The actual OC1A/B value will only be visible on the port pin

if the data direction for the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The

PWM waveform is generated by setting (or clearing) the OC1A/B Register at the compare

match between OCR1A/B and TCNT1 when the counter increments, and clearing (or setting)

the OC1A/B Register at compare match between OCR1A/B and TCNT1 when the counter

decrements. The PWM frequency for the output when using phase and frequency correct

PWM can be calculated by the following equation:

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).

The extreme values for the OCR1A/B Register represents special cases when generating a

PWM waveform output in the phase correct PWM mode. If the OCR1A/B is set equal to BOT-

TOM the output will be continuously low and if set equal to TOP the output will be set to high

for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

12.10 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

T1) is therefore shown as a

clock enable signal in the following figures. The figures include information on when interrupt

flags are set, and when the OCR1A/B Register is updated with the OCR1A/B buffer value

(only for modes utilizing double buffering). Figure 12-11 shows a timing diagram for the setting

of OCF1A/B.

Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1A/B, no Prescaling

Figure 12-12 shows the same timing data, but with the prescaler enabled.

fOCnxPFCPWM

clk_I/O

NTOP

⋅⋅

---------------------------------

clk

(clk

I/O/1)

OCFnx

clk

I/O

OCRnx

TCNTn

OCRnx Value

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

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