AD9548SLASHPCBZ datasheet(104/112 Pages) AD

104 / 112 page

AD9548

Rev. 0 | Page 104 of 112

Table 151. EEPROM Storage Sequence for Operational Control Settings

Address

Bits

Bit Name

Description

0E2F

[7:0]

Operational controls

The default value of this register is 0x10, which the controller interprets as a data

instruction. Its decimal value is 16, which this tells the controller to transfer 17 bytes of

data (16 + 1) beginning at the address specified by the next two bytes. The controller

stores 0x10 in the EEPROM and increments the EEPROM address pointer.

0E30

[7:0]

Operational controls

The default value of these two registers is 0x0A00. Note that Register 0E30 and

address, respectively. Because the previous register contains a data instruction,

these two registers define a starting address (in this case, 0x0A00). The controller

stores 0x0A00 in the EEPROM and increments the EEPROM pointer by 2. It then

transfers 17 bytes from the register map (beginning at Address 0x0A00) to the

EEPROM and increments the EEPROM address pointer by 18 (17 data bytes and

one checksum byte). The 17 bytes transferred correspond to the operational

controls parameters in the register map.

0E31

[7:0]

0E32

[7:0]

I/O update

The default value of this register is 0x80, which the controller interprets as an I/O

update instruction. The controller stores 0x80 in the EEPROM and increments the

EEPROM address pointer.

Table 152. EEPROM Storage Sequence for End of Data

Address

Bits

Bit Name

Description

0E33

[7:0]

End of data

The default value of this register is 0xFF, which the controller interprets as an end

instruction. The controller stores this instruction in the EEPROM, resets the EEPROM

address pointer, and enters an idle state. Note that, if this were a pause rather than an

end instruction, the controller actions would be the same except that the controller

would not reset the EEPROM address pointer.

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