AD9548SLASHPCBZ datasheet(57/112 Pages) AD

57 / 112 page

AD9548

Rev. 0 | Page 57 of 112

Data Transfer Format

Write byte format—the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.

Slave

address

RAM address

high byte

RAM address

low byte

RAM

Data 0

RAM

Data 1

RAM

Data 2

Send byte format—the send byte protocol is used to set up the register address for subsequent reads.

Slave address

RAM address high byte

RAM address low byte

Receive byte format—the receive byte protocol is used to read the data byte(s) from RAM starting from the current address.

Slave address

RAM Data 0

RAM Data 1

RAM Data 2

Read byte format—the combined format of the send byte and the receive byte.

Slave

Address

RAM

Address

High Byte

RAM

Address

Low Byte

Slave

Address

RAM

Data

RAM

Data

RAM

Data

I²C Serial Port Timing

SSr

SDA

SCL

tSP

tHD; STA

tSU; STA

tSU; DAT

tHD; DAT

tHD; STA

tHI

tLO

tSU; STO

tBUF

Figure 64. I²C Serial Port Timing

Table 34. I2C Timing Definitions

Parameter

Description

fSCL

Serial clock

tBUF

Bus free time between stop and start conditions

tHD; STA

Repeated hold time start condition

tSU; STA

Repeated start condition setup time

tSU; STO

Stop condition setup time

tHD; DAT

Data hold time

tSU; DAT

Date setup time

tLO

SCL clock low period

tHI

SCL clock high period

Minimum/maximum receive SCL and SDA rise time

Minimum/maximum receive SCL and SDA fall time

tSP

Pulse width of voltage spikes that must be suppressed by the input filter

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