AD9548SLASHPCBZ datasheet(35/112 Pages) AD

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AD9548

Rev. 0 | Page 35 of 112

DDS Phase Offset

The relative phase of the sinusoid generated by the DDS is

numerically controlled by adding a phase offset word to the output

of the DDS accumulator. This is accomplished via the open loop

phase offset register (Address 030D to Address 030E), which is

a programmable 16-bit value (Δphase). The resulting phase offset,

ΔΦ (in radians), is given by

⎟

⎠

⎞

⎜

⎝

⎛ Δ

phase

Phase offset and relative time offset are directly related. The

time offset is (Δphase/216)/fDDS (in seconds), where fDDS is the

output frequency of the DDS (in hertz).

DAC Output

The output of the digital core of the DDS is a time series of

numbers representing a sinusoidal waveform. The DAC

translates the numeric values to an analog signal. The DAC

output signal appears at two pins that constitute a balanced

current source architecture (see Figure 43).

CURRENT

SWITCH

ARRAY

SWITCH

CONTROL

IFS

ISCALE

AVDD3

DACOUTP

DACOUTN

CURRENT

MIRROR

GND

CODE

Ω

IFS (1–

)

214 – 1

CODE

IFS (

)

214 – 1

Figure 43. DAC Output Pins

The value of IFS is programmable via the 10-bit DAC full-scale

current word in the DAC current register (Address 0213 to

Address 0214). The value of the 10-bit word (ISCALE) sets IFS

according to the following formula:

()

SCALE

μA

120

TUNING WORD PROCESSING

The frequency tuning words that dictate the output frequency

of the DDS come from one of three sources (see Figure 44).

•

The free running frequency tuning word register

•

The output of the digital loop filter

•

The output of the tuning word history processor

TUNING WORD

HISTORY

PROCESSOR

TUNING WORD

HISTORY

FREE-RUN

TUNING WORD

UPDATE

FROM DIGITAL

LOOP FILTER

TO DDS

TUNING

WORD

ROUTING

CONTROL

TUNING

WORD

CLAMP

LOWER

TUNING

WORD

UPPER

TUNING

WORD

Figure 44. Tuning Word Processing

When the DPLL is in free-run mode, the DDS tuning word is

the value stored in the free running frequency tuning word

operating normally (closed loop), the DDS tuning word comes

from the output of the digital loop filter, which changes

dynamically in order to maintain phase lock with the input

reference signal (assuming that the device has not performed an

automatic switch to holdover mode). When the DPLL is in

holdover mode, the DDS tuning word depends on a historical

record of past tuning words during the time that the DPLL

operated in closed-loop mode.

However, regardless of the operating mode, the DDS output

frequency is ultimately subject to the boundary conditions

imposed by the frequency clamp logic, as explained in the

Frequency Clamp section.

Frequency Clamp

The user controls the frequency clamp boundaries via the pull-

in range limits registers (Address 0307 to Address 030C). These

registers allow the user to fix the DDS output frequency

between an upper and lower bound with a granularity of 24 bits.

Note that these upper and lower bounds apply regardless of the

frequency tuning word that appears at the input to the DDS.

The register value relates to the absolute upper or lower

frequency bound (fCLAMP) as

fCLAMP = fS × (N/224)

Where N is the value stored in the upper- or lower-limit

Even though the frequency clamp limits put a bound on the

DDS output frequency, the DPLL is still free to steer the DDS

frequency within the clamp limits. The default register values

set the clamp range from 0 Hz (dc) to fS, effectively eliminating

the frequency clamp functionality until the user alters the

Frequency Tuning Word History

The AD9548 has the ability to track the history of the tuning

word samples generated by the DPLL digital loop filter output.

It does so by periodically computing the average tuning word

value over a user-specified interval. The user programs the

interval via the 24-bit history accumulation timer register

(Address 0318 to Address 031A). This 24-bit value represents

a time interval (TAVG) in milliseconds that extends from 1 ms to

a maximum of 4:39:37.215 (hr:min:sec).

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