AD9548SLASHPCBZ datasheet(99/112 Pages) AD

99 / 112 page

AD9548

Rev. 0 | Page 99 of 112

Address

Bits

Bit Name

Description

0D07

[7]

Ref BB new profile

Indicates that Ref BB has switched to a new profile

[6]

Ref BB validated

Indicates that Ref BB has been validated

[5]

Ref BB fault cleared

Indicates that Ref BB has been cleared of a previous fault

[4]

Ref BB fault

Indicates that Ref BB has been faulted

[3]

Ref B new profile

Indicates that Ref B has switched to a new profile

[2]

Ref B validated

Indicates that Ref B has been validated

[1]

Ref B fault cleared

Indicates that Ref B has been cleared of a previous fault

[0]

Ref B fault

Indicates that Ref B has been faulted

0D08

[7]

Ref CC new profile

Indicates that Ref CC has switched to a new profile

[6]

Ref CC validated

Indicates that Ref CC has been validated

[5]

Ref CC fault cleared

Indicates that Ref CC has been cleared of a previous fault

[4]

Ref CC fault

Indicates that Ref CC has been faulted

[3]

Ref C new profile

Indicates that Ref C has switched to a new profile

[2]

Ref C validated

Indicates that Ref C has been validated

[1]

Ref C fault cleared

Indicates that Ref C has been cleared of a previous fault

[0]

Ref C fault

Indicates that Ref C has been faulted

0D09

[7]

Ref DD new profile

Indicates that Ref DD has switched to a new profile

[6]

Ref DD validated

Indicates that Ref DD has been validated

[5]

Ref DD fault cleared

Indicates that Ref DD has been cleared of a previous fault

[4]

Ref DD fault

Indicates that Ref DD has been faulted

[3]

Ref D new profile

Indicates that Ref D has switched to a new profile

[2]

Ref D validated

Indicates that Ref D has been validated

[1]

Ref D fault cleared

Indicates that Ref D has been cleared of a previous fault

[0]

Ref D fault

Indicates that Ref D has been faulted

Table 137. DPLL Status

Address

Bits

Bit Name

Description

0D0A

[7]

Offset slew limiting

The current closed-loop phase offset is rate limited.

[6]

Phase build-out

A phase build-out transition was made to the currently active reference.

[5]

Freq lock

The DPLL has achieved frequency lock.

[4]

Phase lock

The DPLL has achieved phase lock.

[3]

Loop switching

The DPLL is in the process of a reference switchover.

[2]

Holdover

The DPLL is in holdover mode.

[1]

Active

The DPLL is active (that is, operating in a closed-loop condition)

[0]

Free running

The DPLL is free running (that is, operating in an open-loop condition)

0D0B

[7]

Frequency clamped

The upper or lower frequency tuning word clamp is in effect.

[6]

History available

There is sufficient tuning word history available for holdover operation.

[5:3]

Active reference

priority

Priority value of the currently active reference.

000 = highest priority.

111 = lowest priority.

[2:0]

Active reference

Index of the currently active reference.

000 = Reference A.

001 = Reference AA.

010 = Reference B.

011 = Reference BB.

100 = Reference C.

101 = Reference CC.

110 = Reference D.

111 = Reference DD.

AD9548/PCBZ датащи(PDF) 99 Page - Analog Devices

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