AD9548SLASHPCBZ datasheet(78/112 Pages) AD

78 / 112 page

AD9548

Rev. 0 | Page 78 of 112

Table 67. Distribution Synchronization

Address

Bits

Bit Name

Description

0402

[7:6]

Unused

[5:4]

Sync source

Select the sync source for the clock distribution output channels.

00 (default) = direct.

01 = active reference.

10 = DPLL feedback edge.

11 = reserved.

[3]

OUT3 sync mask

Mask the synchronous reset to the OUT3 divider.

0 (default) = unmasked

1 = masked.

[2]

OUT2 sync mask

Mask the synchronous reset to the OUT2 divider.

0 (default) = unmasked.

1 = masked.

[1]

OUT1 sync mask

Mask the synchronous reset to the OUT1 divider.

0 (default) = unmasked.

1 = masked.

[0]

OUT0 sync mask

Mask the synchronous reset to the OUT0 divider.

0 (default) = unmasked.

1 = masked.

Table 68. Automatic Synchronization

Address

Bits

Bit Name

Description

0403

[7:2]

Unused

[1:0]

Automatic sync mode

Autosync mode

00 (default) = disabled

01 = sync on DPLL frequency lock

10 = sync on DPLL phase lock

11 = reserved

Table 69. Distribution Channel Modes

Address

Bits

Bit Name

Description

0404

[7:6]

Unused

[5]

OUT0 CMOS phase

invert

When the output mode is CMOS, the bit inverts the relative phase between the two

CMOS output pins. Otherwise, this bit is nonfunctional.

0 (default) = not inverted.

1 = inverted.

[4]

OUT0 polarity invert

Invert the polarity of OUT0.

0 (default) = not inverted.

1 = inverted.

[3]

OUT0 drive strength

OUT0 output drive capability control.

0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal.

1 = CMOS: normal drive strength; LVDS: 7 mA nominal.

[2:0]

OUT0 mode

OUT0 operating mode select.

000 = CMOS (both pins)

001 = CMOS (positive pin), tristate (negative pin).

010 = tristate (positive pin), CMOS (negative pin).

011 (default) = tristate (both pins).

100 = LVDS.

101 = LVPECL.

110 = reserved.

111 = reserved.

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