AD9548SLASHPCBZ datasheet(16/112 Pages) AD

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AD9548

Rev. 0 | Page 16 of 112

Pin No.

Mnemonic

Input/

Output

Pin Type

Description

23, 24

AVDD

Power

1.8 V Analog (DAC) Power Supply.

CLKINN

Differential

input

Clock Distribution Input. In standard operating mode, this pin is connected to the

filtered DACOUTN output. This internally biased input is typically ac-coupled and,

when configured as such, can accept any differential signal whose single-ended

swing is at least 400 mV.

CLKINP

Differential

input

Clock Distribution Input. In standard operating mode, this pin is connected to the

filtered DACOUTP output

AVDD

Power

1.8 V Analog (Input Receiver) Power Supply.

OUT_RSET

Current set

resistor

Connect an optional 3.12 kΩ resistor from this pin to ground (see the Output

Current Control with an External Resistor section).

31, 37, 38,

AVDD3

Power

Analog Supply for Output Driver. These pins are normally 3.3 V but can be 1.8 V.

Pin 31 powers Out0x. Pin 37 powers OUT1x. Pin 38 powers OUT2x. Pin 44 powers

OUT3x. Apply power to these pins even if the corresponding outputs (OUT0P/

OUT0N, OUT1P/ OUT1N, OUT2P/ OUT2N, and OUT3P/ OUT3N) are not used. See

the Power Supply Partitions section.

OUT0P

LVPECL,

LVDS, or

CMOS

Output 0. This output can be configured as LVPECL, LVDS, or single-ended CMOS.

LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS

operation can be either 1.8 V or 3.3 V, depending on the output driver power

supply.

OUT0N

LVPECL,

LVDS, or

CMOS

Complementary Output 0. This output can be configured as LVPECL, LVDS, or

single-ended CMOS.

34, 41

AVDD

Power

1.8 V Analog (Output Divider) Power Supply.

OUT1P

LVPECL,

LVDS, or

CMOS

Output 1. This output can be configured as LVPECL, LVDS, or single-ended CMOS.

LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS

operation can be either 1.8 V or 3.3 V, depending on the output driver power

supply.

OUT1N

LVPECL,

LVDS, or

CMOS

Complementary Output 1. This output can be configured as LVPECL, LVDS, or

single-ended CMOS.

OUT2P

LVPECL,

LVDS, or

CMOS

Output 2. This output can be configured as LVPECL, LVDS, or single-ended CMOS.

LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS

operation can be either 1.8 V or 3.3 V, depending on the output driver power

supply.

OUT2N

LVPECL,

LVDS, or

CMOS

Complementary Output 2. This output can be configured as LVPECL, LVDS, or

single-ended CMOS.

OUT3P

LVPECL,

LVDS, or

CMOS

Output 3. This output can be configured as LVPECL, LVDS, or single-ended CMOS.

LVPECL and LVDS operation require a 3.3 V output driver power supply. CMOS

operation can be either 1.8 V or 3.3 V, depending on the output driver power

supply.

OUT3N

LVPECL,

LVDS, or

CMOS

Complementary Output 3. This output can be configured as LVPECL, LVDS, or

single-ended CMOS.

AVDD3

Power

3.3 V Analog (System Clock) Power Supply.

SYSCLK_VREG

System Clock Loop Filter Voltage Regulator. Connect a 0.1 μF capacitor from this

pin to ground. This pin is also the ac ground reference for the integrated SYSCLK

PLL multiplier’s external loop filter (see the SYSCLK PLL Multiplier section).

SYSCLK_LF

System Clock Multiplier Loop Filter. When using the frequency multiplier to drive

the system clock, an external loop filter can be attached to this pin.

50, 55

AVDD

Power

1.8 V Analog (System Clock) Power Supply.

SYSCLKN

Differential

input

Complementary System Clock Input. Complementary signal to SYSCLKP. SYSCLKN

contains internal dc biasing and should be ac-coupled with a

0.01 μF capacitor, except when using a crystal, in which case connect the crystal

across SYSCLKP and SYSCLKN.

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