AD9548SLASHPCBZ datasheet(47/112 Pages) AD

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AD9548

Rev. 0 | Page 47 of 112

Table 26. EEPROM Controller Instruction Set

Instruction

Value (Hex)

Instruction Type

Bytes

Required

Description

00 to 7F

Data

A data instruction tells the controller to transfer data to or from the device settings

part of the register map. A data instruction requires two additional bytes that

together indicate a starting address in the register map. Encoded in the data

instruction is the number of bytes to transfer, which is one more than the

instruction value.

I/O update

When the controller encounters this instruction while downloading from the

EEPROM, it issues a soft I/O update (see Register 0005 in Table 41).

Calibrate

When the controller encounters this instruction while downloading from the

EEPROM, it initiates a system clock calibration sequence (see Register 0A02 in Table

120).

Distribution sync

When the controller encounters this instruction while downloading from the

EEPROM, it issues a sync pulse to the output distribution synchronization (see

B0 to CF

Condition

B1 to CF are condition instructions and correspond to Condition 1 through

Condition 31, respectively. B0 is the null condition instruction. See the EEPROM

Conditional Processing section for details.

Pause

When the controller encounters this instruction in the scratch pad while uploading

to the EEPROM, it resets the scratch pad address pointer and holds the EEPROM

address pointer at its last value. This allows storage of more than one instruction

sequence in the EEPROM. Note that the controller does not copy this instruction to

the EEPROM during upload.

End

When the controller encounters this instruction in the scratch pad while uploading

to the EEPROM, it resets both the scratch pad address pointer and the EEPROM

address pointer and then enters an idle state.

When the controller encounters this instruction while downloading from the

EEPROM, it resets the EEPROM address pointer and then enters an idle state.

EEPROM Instructions

Table 26 lists the EEPROM controller instruction set. The

controller recognizes all instruction types whether it is in

upload or download mode, except for the pause instruction,

which it only recognizes in upload mode.

The I/O update, calibrate, distribution sync, and end instruct-

tions are mostly self-explanatory. The others, however, warrant

further detail, as described in the following paragraphs.

Data instructions are those that have a value from 00 to 7F. A

data instruction tells the controller to transfer data between

the EEPROM and the register map. The controller needs the

following two parameters to carry out the data transfer:

•

The number of bytes to transfer

•

The register map target address

The controller decodes the number of bytes to transfer directly

from the data instruction itself by adding one to the value of the

instruction. For example, the data instruction, 1A, has a decimal

value of 26; therefore, the controller knows to transfer 27 bytes

(one more than the value of the instruction). Whenever the

controller encounters a data instruction, it knows to read the

next two bytes in the scratch pad because these contain the

Note that, in the EEPROM scratch pad, the two registers that

comprise the address portion of a data instruction have the

MSB of the address in the D7 position of the lower register

address. The bit weight increases left to right, from the lower

starting address always indicates the lowest numbered register

map address in the range of bytes to transfer. That is, the

controller always starts at the register map target address and

counts upward regardless of whether the serial I/O port is

operating in I2C, SPI LSB-first, or SPI MSB-first mode.

As part of the data transfer process during an EEPROM upload,

the controller calculates a 1-byte checksum and stores it as the

final byte of the data transfer. As part of the data transfer process

during an EEPROM download, however, the controller again

calculates a 1-byte checksum value but compares the newly

calculated checksum with the one that was stored during the

upload process. If an upload/download checksum pair does not

match, the controller sets the EEPROM fault status bit. If the

upload/download checksums match for all data instructions

encountered during a download sequence, the controller sets

the EEPROM complete status bit.

Condition instructions are those that have a value from B0 to

CF. Condition instructions B1 to CF represent Condition 1 to

Condition 31, respectively. The B0 condition instruction is

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