AD9548SLASHPCBZ datasheet(36/112 Pages) AD

36 / 112 page

AD9548

Rev. 0 | Page 36 of 112

Note that history accumulation timer = 0 should not be

programmed because it may cause improper device operation.

The control logic performs a calculation of the average tuning

word during the TAVG interval and stores the result in the

holdover history register (Address 0D14 to Address 0D19).

Computation of the average for each TAVG interval is

independent of the previous interval (that is, the average is a

memoryless average as opposed to a true moving average). In

addition, at the end of each TAVG interval, the device generates

an internal strobe pulse. The strobe pulse sets the history

updated bit in the IRQ monitor register (assuming the bit is

enabled via the IRQ mask register). Furthermore, the strobe

pulse is available as an output signal via the multifunction pins

(see the Multifunction Pins (M0 to M7) section).

History accumulation begins whenever the device switches to a

new reference. By default, the device clears any previous history

when it switches to a new reference. Furthermore, the user can

clear the tuning word history under software control via

multifunction pins (see the Multifunction Pins (M0 to M7)

section). However, the user has the option of programming the

device to retain (rather than clear) the old history by setting the

persistent history bit (Register 031B, Bit 3).

Whenever the tuning word history is nonexistent (that is, after a

power-up, reset, or switchover to a new reference with the

persistent history bit cleared), the device waits for the history

accumulation timer (TAVG) to expire before storing the first

history value in the holdover history register.

In cases where TAVG is quite large (4½ hours, for example), a

problem arises in that the first averaged result does not become

available until the full TAVG interval passes. Thus, it is possible

that as much as 4½ hours can elapse before the first averaged

result is available. If the device has to switch to holdover mode

during this time, a tuning word history is not available.

To alleviate this problem, the user has access to the incremental

average bits in the history mode register (Register 031B,

Bits[2:0]). If the history has been cleared, then this 3-bit value,

K (0 ≤ K ≤ 7), specifies the number of intermediate averages to

take during the first, and only the first, TAVG interval. When

K = 0, no intermediate averages are calculated; therefore, the

first average occurs after interval TAVG (the default operating

mode). However, if K = 4, for example, four intermediate

averages are taken during the first TAVG interval.

These average computations occur at TAVG/16, TAVG/8, TAVG/4,

TAVG/2, and TAVG (notice that the denominator exhibits a

sequence of powers of 2 beginning with TAVG/2K). The calcu-

lation of intermediate averages occurs only during the first

TAVG interval. All subsequent average computations occur at

evenly spaced intervals of TAVG.

LOOP CONTROL STATE MACHINE

The loop control state machine is responsible for monitoring,

initiating, and sequencing changes to the DPLL loop. Generally,

it automatically controls the transition between input references

and the entry and exit of holdover mode. In controlling loop

state changes, the state machine also arbitrates the application

of new loop filter coefficients, divider settings, and phase

detector offsets based on the profile settings. The user can

manually force the device into holdover or free-run mode via

the loop mode register (Address 0A01), as well as force the

selection of a specific input reference.

Switchover

Switchover occurs when the loop controller switches directly

from one input reference to another. Functionally, the AD9548

handles a reference switchover by briefly entering holdover

mode and then immediately recovering. During the switchover

event, however, the AD9548 preserves the status of the lock

detectors to avoid phantom unlock indications.

Holdover

The holdover state of the DPLL is an open-loop operating

mode. That is, the device no longer operates as a closed-loop

system. Instead, the output frequency remains constant and is

dependent on the device programming and availability of

tuning word history.

If a tuning word history exists (see the Frequency Tuning Word

History section), then the holdover frequency is the average

frequency just prior to entering the holdover state. If there is no

tuning word history, then the holdover frequency depends on

the state of the single sample fallback bit in the history mode

Logic 0, then the holdover frequency is the frequency defined in

the free running frequency tuning word register (Address 0300

to Address 0305). If the single sample fallback bit is Logic 1, then

the holdover frequency is the last instantaneous frequency output

by the DDS just prior to the device entering holdover mode

(note that this is not the average frequency prior to holdover).

The initial holdover frequency accuracy depends on the loop

bandwidth of the DPLL and the time elapsed to compute a

tuning word history. The longer the historical average, the more

accurate the initial holdover frequency (assuming a drift-free

system clock). Furthermore, the stability of the system clock

establishes the stability and long-term accuracy of the holdover

output frequency. Another consideration is the 48-bit frequency

tuning resolution of the DDS and its relationship to fractional

frequency error, ΔfO/fO, as follows:

where, fS is the sample rate of the output DAC, and fO is the DDS

output frequency.

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