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AD9548/PCBZ датащи(PDF) 44 Page - Analog Devices

номер детали AD9548/PCBZ
подробное описание детали  Quad/Octal Input Network Clock Generator/Synchronizer
PDF  112 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9548/PCBZ датащи(HTML) 44 Page - Analog Devices

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AD9548
Rev. 0 | Page 44 of 112
STATUS AND CONTROL
MULTIFUNCTION PINS (M0 TO M7)
The AD9548 has eight digital CMOS I/O pins (M0 to M7) that
are configurable for a variety of uses. The function of these pins
is programmable via the register map. Each pin can control or
monitor an assortment of internal functions based on the contents
of Register 0200 to Register 0207. To monitor an internal function
with a multifunction pin, write a Logic 1 to the most significant
bit of the register associated with the desired multifunction pin.
The value of the seven least significant bits of the register defines
the control function, as shown in Table 24.
Table 24. Multifunction Pin Output Functions, Register 0200
to Register 0207 (Bit 7 = 1)
Bits[6:0]
Value
Output Function
Source Proxy
0
Static Logic 0
1
Static Logic 1
2
System clock divided
by 32
3
Watchdog timer
output
4
EEPROM upload in
progress
Register 0D00, Bit 0
5
EEPROM download in
progress
Register 0D00, Bit 1
6
EEPROM fault detected
Register 0D00, Bit 2
7
SYSCLK PLL lock
detected
Register 0D01, Bit 0
8
SYSCLK PLL calibration
in progress
Register 0D01, Bit 1
9
Unused
10
Unused
11
SYSCLK PLL stable
Register 0D01, Bit 4
12 to 15
Unused
16
DPLL free running
Register 0D0A, Bit 0
17
DPLL active
Register 0D0A, Bit 1
18
DPLL in holdover
Register 0D0A, Bit 2
19
DPLL in reference
switchover
Register 0D0A, Bit 3
20
Active reference: phase
master
Register 0D0A, Bit 6
21
DPLL phase locked
Register 0D0A, Bit 4
22
DPLL frequency locked
Register 0D0A, Bit 5
23
DPLL phase slew
limited
Register 0D0A, Bit 7
24
DPLL frequency
clamped
Register 0D0B, Bit 7
25
Tuning word history
available
Register 0D0B, Bit 6
26
Tuning word history
updated
Register 0D05, Bit 4
27 to 31
Unused
32
Reference A fault
Register 0D0C, Bit 2
33
Reference AA fault
Register 0D0D, Bit 2
Bits[6:0]
Value
Output Function
Source Proxy
34
Reference B fault
Register 0D0E, Bit 2
35
Reference BB fault
Register 0D0F, Bit 2
36
Reference C fault
Register 0D10, Bit 2
37
Reference CC fault
Register 0D11, Bit 2
38
Reference D fault
Register 0D12, Bit 2
39
Reference DD fault
Register 0D13, Bit 2
40 to 47
Unused
48
Reference A valid
Register 0D0C, Bit 3
49
Reference AA valid
Register 0D0D, Bit 3
50
Reference B valid
Register 0D0E, Bit 3
51
Reference BB valid
Register 0D0F, Bit 3
52
Reference C valid
Register 0D10, Bit 3
53
Reference CC valid
Register 0D11, Bit 3
54
Reference D valid
Register 0D12, Bit 3
55
Reference DD valid
Register 0D13, Bit 3
56 to 63
Unused
64
Reference A active
eference
Register 0D0B, Bits[2:0]
65
Reference AA active
reference
Register 0D0B, Bits[2:0]
66
Reference B active
reference
Register 0D0B, Bits[2:0]
67
Reference BB active
reference
Register 0D0B, Bits[2:0]
68
Reference C active
reference
Register 0D0B, Bits[2:0]
69
Reference CC active
reference
Register 0D0B, Bits[2:0]
70
Reference D active
reference
Register 0D0B, Bits[2:0]
71
Reference DD active
reference
Register 0D0B, Bits[2:0]
72 to 79
Unused
80
Clock distribution sync
pulse
Register 0D03, Bit 3
81 to 127
Unused
To control an internal function with a multifunction pin, write a
Logic 0 to the most significant bit of the register associated with
the desired multifunction pin. The monitored function depends
on the value of the seven least significant bits of the register, as
shown in Table 25.
Table 25. Multifunction Pin Input Functions, Register 0200
to Register 0207 (Bit 7 = 0)
Bits[6:0]
Value
Output Function
Destination Proxy
0
Unused (default)
1
I/O update
Register 0005, Bit 0
2
Full power-down
Register 0A00, Bit 0
3
Watchdog reset
Register 0A03, Bit 0
4
IRQ reset
Register 0A03, Bit 1



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