AD9548SLASHPCBZ datasheet(37/112 Pages) AD

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AD9548

Rev. 0 | Page 37 of 112

System Clock Period

The worst-case scenario is maximum fS (1 GHz) and minimum fO

(62.5 MHz), which yields ΔfO/fO = 2.8 × 10−14, less than one part

in 10 trillion.

Many of the user-programmable parameters of the AD9548 have

absolute time units. To make this possible, the AD9548 requires

a priori knowledge of the period of the system clock. To accom-

modate this requirement, the user programs the 21-bit nominal

system clock period in the nominal SYSCLK period register

(Address 0106 to Address 0108). The contents of this register

reflect the actual period of the system clock in femtoseconds.

The user must properly program this register to ensure proper

operation of the device because many of its subsystems rely on

this value.

Recovery from Holdover

When in holdover and a valid reference becomes available, the

device exits holdover operation. The loop state machine restores

the DPLL to closed-loop operation, locks to the selected

reference, and sequences the recovery of all the loop parameters

based on the profile settings for the active reference.

Note that, if the user holdover bit (Register 0A01, Bit 6) is set,

the device does not automatically exit holdover when a valid

reference is available. However, automatic recovery can occur

after clearing the user holdover bit.

System Clock Details

A block diagram of the system clock appears in Figure 45. The

signal at the SYSCLKx input pins becomes the internally

buffered DAC sampling clock (fS) via one of three paths.

SYSTEM CLOCK INPUTS

Functional Description

•

High frequency direct (HF)

The system clock circuit provides a low jitter, stable, high

frequency clock for use by the rest of the chip. The user has the

option of directly driving the SYSCLKx inputs with a high

frequency clock source at the desired system clock rate.

Alternatively, the SYSCLKx input can be configured to operate

in conjunction with the internal SYSCLK PLL. The SYSCLK

PLL can synthesize the system clock by means of a crystal

resonator connected across the SYSCLKx input pins or by

means of direct application of a low frequency clock source.

•

Low frequency synthesized (LF)

•

Crystal resonator synthesized (XTAL)

Note that both the LF and XTAL paths require the use of the

SYSCLK PLL (see the SYSCLK PLL Multiplier section).

The main purpose of the HF path is to allow the direct use of a

high frequency (500 MHz to 1 GHz) external clock source for

clocking the AD9548. This path is optimized for high frequency

and low noise floor. Note that the HF input also provides a path

to SYSCLK PLL (see the SYSCLK PLL Multiplier section),

which includes an input divider (M) programmable for divide-

by -1, -2, -4, or -8. The purpose of the divider is to limit the

frequency at the input to the PLL to less than 150 MHz (the

maximum PFD rate).

The SYSCLKx inputs are internally biased to a dc level of ~1 V.

Take care to ensure that any external connections do not disturb

the dc bias because this may significantly degrade performance.

Generally, the recommendation is that the SYSCLKx inputs be

ac-coupled to the signal source (except when using a crystal

resonator).

2×

÷N

VCO

CALIBRATION

LOCK

DETECT

SYSTEM

CLOCK

÷M

LOOP

FILTER

SYSCLKN

SYSCLKP

SYSCLK_VREG

SYSCLK_LF

XTAL

PFD

AND

CHARGE

PUMP

Figure 45. System Clock Block Diagram

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