AD9548SLASHPCBZ datasheet(34/112 Pages) AD

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AD9548

Rev. 0 | Page 34 of 112

DIRECT DIGITAL SYNTHESIZER

draining, the water level in the tub eventually rises above the

high water mark (+1024), which causes the phase lock detector

to indicate lock. If more draining is taking place than filling,

then the water level in the tub eventually falls below the low

water mark (−1024), which causes the phase lock detector to

indicate unlock. The ability to specify the threshold level, fill

rate, and drain rate enables the user to tailor the operation of

the phase lock detector to the statistics of the timing jitter

associated with the input reference signal.

DDS Overview

One of the primary building blocks of the digital PLL is a direct

digital synthesizer (DDS). The DDS behaves like a sinusoidal

signal generator. The frequency of the sinusoid generated by the

DDS is determined by a frequency tuning word (FTW), which

is a digital (that is, numeric) value. Unlike an analog sinusoidal

generator, a DDS uses digital building blocks and operates as a

sampled system. Thus, it requires a sampling clock (fS) that

serves as the fundamental timing source of the DDS. The

accumulator behaves as a modulo-248 counter with a

programmable step size (FTW). A block diagram of the DDS

appears in Figure 42.

2048

–2048

1024

–1024

LOCK LEVEL

UNLOCK LEVEL

LOCKED

UNLOCKED

STATE

FILL

RATE

DRAIN

RATE

The input to the DDS is the 48-bit FTW. The FTW serves as a

step size value. On each cycle of fS, the accumulator adds the

value of the FTW to the running total at its output. For

example, given FTW = 5, the accumulator counts by fives,

incrementing on each fS cycle. Over time, the accumulator

reaches the upper end of its capacity (248 in this case), at which

point, it rolls over but retains the excess. The average rate at

which the accumulator rolls over establishes the frequency of

the output sinusoid. The average rollover rate of the accumulator

establishes the output frequency (fDDS) of the DDS and is given by

Figure 41. Lock Detector Diagram

Note that whenever the AD9548 enters the free-run or holdover

mode, the DPLL phase lock detector indicates unlocked. In

addition, whenever the AD9548 performs a reference switch-

over, the state of the lock detector prior to the switch is

preserved during the transition period.

DPLL Frequency Lock Detector

DDS

FTW

⎟

⎠

⎞

⎜

⎝

⎛

The operation of the frequency lock detector is identical to that

of the phase lock detector. The only difference is that the fill or

drain decision is based on the period deviation between the

reference and feedback signals of the DPLL instead of the phase

error at the output of the PFD.

Solving this equation for FTW yields

⎥

⎦

⎤

⎢

⎣

⎡

⎟

⎠

⎞

⎜

⎝

⎛

DDS

FTW

round

The frequency lock detector uses a 24-bit frequency threshold

threshold value extends from 0 μs to ±16.777215 μs. It represents

the magnitude of the difference in period between the reference

and feedback signals at the input to the DPLL. For example, if

the reference signal is 1.25 MHz and the feedback signal is 1.38

MHz, then the period difference is approximately 75.36 ns

(|1/1,250,000 − 1/1,380,000| ≈ 75.36 ns).

For example, given that fS = 1 GHz and fDDS = 155.52 MHz, then

FTW = 437,749,988,378,041 (0x27D028A1DFB9).

Note that the minimum DAC output frequency is 62.5 MHz;

therefore, normal operation requires an FTW that yields an

output frequency in excess of this lower bound.

DAC

(14-BIT)

PHASE

OFFSET

FREQUENCY

TUNING WORD

(FTW)

DAC+

DAC–

ANGLE TO

AMPLITUDE

CONVERSION

48-BIT ACCUMULATOR

Figure 42. DDS Block Diagram

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