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AD9548

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I²C SERIAL PORT OPERATION

The I2C interface has the advantage of requiring only two control

pins and is a de facto standard throughout the I2C industry. However,

its disadvantage is programming speed, which is 400 kbps maximum.

The AD9548 I2C port design is based on the I2C fast mode standard

from Philips, so it supports both the 100 kHz standard mode and

400 kHz fast mode. Fast mode imposes a glitch tolerance requirement

on the control signals. That is, the input receivers ignore pulses of

less than 50 ns duration.

The AD9548 I2C port consists of a serial data line (SDA) and a

serial clock line (SCL). In an I2C bus system, the AD9548 is

connected to the serial bus (data bus SDA and clock bus SCL)

as a slave device; that is, no clock is generated by the AD9548.

The AD9548 uses direct 16-bit memory addressing instead of

traditional 8-bit memory addressing.

The AD9548 allows up to seven unique slave devices to occupy

the I2C bus. These are accessed via a 7-bit slave address

transmitted as part of an I2C packet. Only the device with a

matching slave address responds to subsequent I2C commands.

The device slave address is 1001xxx (the three right bits are

determined by the M0 to M2 pins). The four MSBs (1001) are

hard-wired, while the three LSBs (xxx, determined by the M0 to

M2 pins) are programmable via the power-up state of the

multifunction pins (see the Initial Pin Programming section).

I2C Bus Characteristics

A summary of the various I2C protocols appears in Table 33.

Table 33. I2C Bus Abbreviation Definitions

Abbreviation

Definition

Start

Repeated start

Stop

Acknowledge

Nonacknowledge

Write

Read

The transfer of data is shown in Figure 59. One clock pulse is

generated for each data bit transferred. The data on the SDA line

must be stable during the high period of the clock. The high or

low state of the data line can only change when the clock signal on

the SCL line is low.

DATA LINE

STABLE;

DATA VALID

CHANGE

OF DATA

ALLOWED

SDA

SCL

Figure 59. Valid Bit Transfer

Start/stop functionality is shown in Figure 60. The start condition

is characterized by a high-to-low transition on the SDA line while

SCL is high. The start condition is always generated by the master

to initialize a data transfer. The stop condition is characterized by

a low-to-high transition on the SDA line while SCL is high. The

stop condition is always generated by the master to terminate a

data transfer. Every byte on the SDA line must be eight bits long. Each

byte must be followed by an acknowledge bit; bytes are sent MSB first.

SDA

START CONDITION

STOP CONDITION

SCL

Figure 60. Start and Stop Conditions

3 TO 7

SDA

SCL

MSB

ACK FROM

SLAVE-RECEIVER

ACK FROM

SLAVE-RECEIVER

Figure 61. Acknowledge Bit

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