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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9548/PCBZ датащи(PDF) 15 Page - Analog Devices |
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AD9548/PCBZ датащи(HTML) 15 Page - Analog Devices |
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15 / 112 page  AD9548 Rev. 0 | Page 15 of 112 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DVDD SCLK/SCL SDIO SDO DVDD DVDD3 TCLK TMS TDO TDI DVDD RESET DVDD DVDD NC 17 VSS 18 DACOUTP 19 DACOUTN 20 VSS 58 57 56 55 54 53 52 51 50 49 48 47 46 45 59 60 61 62 63 64 65 66 AD9548 TOP VIEW (Not to Scale) 21 AVDD3 22 AVDD3 NC AVDD TDC_VRT TDC_VRB NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS). REFB REFBB SYSCLK_VREG AVDD3 AVDD AVDD SYSCLKN SYSCLKP VSS VSS REFA REFAA AVDD AVDD3 AVDD3 SYSCLK_LF NC NC 88-LEAD LFCSP 12mm × 12mm 0.5mm PITCH CS/SDA Figure 2. 88-Lead LFCSP Pin Configuration Table 21. Pin Function Descriptions Pin No. Mnemonic Input/ Output Pin Type Description 1, 6, 12, 77, 83, 88 DVDD I Power 1.8 V Digital Supply. 2 SCLK/SCL I 3.3 V CMOS Serial Programming Clock. Data clock for serial programming. 3 SDIO I/O 3.3 V CMOS Serial Data Input/Output. When the device is in 4-wire mode, data is written via this pin. In 3-wire mode, both data reads and writes occur on this pin. There is no internal pull-up/pull-down resistor on this pin. 4 SDO O 3.3 V CMOS Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode). There is no internal pull-up/pull-down resistor on this pin. 5 CS/SDA I 3.3 V CMOS Chip Select (SPI). Active low. When programming a device, this pin must be held low. In systems where more than one AD9548 is present, this pin enables individual programming of each AD9548 (in I2C® mode, this is a serial data pin). This pin has an internal 10 kΩ pull-up resistor but only in SPI mode. 7, 82 DVDD3 I Power 3.3 V I/O Digital Supply. 8 TCLK I JTAG Clock. Internal pull-down resistor; no connection if JTAG is not used. 9 TMS I JTAG Mode. Internal pull-up resistor; no connection if JTAG is not used. 10 TDO O JTAG Output. No connection if JTAG is not used 11 TDI I JTAG Input. Internal pull-up resistor; no connection if JTAG is not used. 13 RESET I 3.3 V CMOS Chip Reset. When this active high pin is asserted, the chip goes into reset. This pin has an internal 50 kΩ pull-down resistor. 14, 15 DVDD I Power 1.8 V DAC Decode Digital Supply. Keep isolated from the 1.8 V core digital supply. 16, 45, 46 NC No Connect. 17, 20, 25, 28, 51, 54 VSS O Ground Analog Ground. Connect to ground. 18 DACOUTP O Differential output DAC Output. DACOUTP contains an internal 50 Ω pull-down resistor. 19 DACOUTN O Differential output Complementary DAC Output. DACOUTN contains an internal 50 Ω pull-down resistor. 21, 22 AVDD3 I Power 3.3 V Analog (DAC) Power Supply. |
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