AD9548SLASHPCBZ datasheet(101/112 Pages) AD

101 / 112 page

AD9548

Rev. 0 | Page 101 of 112

EEPROM STORAGE SEQUENCE (REGISTER 0E10 TO REGISTER 0E3F)

The default settings of Register 0E10 to Register 0E33 embody a sample scratch pad instruction sequence. The following is a description of the

Table 141. EEPROM Storage Sequence for System Clock Settings

Address

Bits

Bit Name

Description

0E10

[7:0]

System clock

The default value of this register is 0x08, which the controller interprets as a data

instruction. Its decimal value is 8, which tells the controller to transfer nine bytes of

data (8 + 1) beginning at the address specified by the next two bytes. The controller

stores 0x08 in the EEPROM and increments the EEPROM address pointer.

0E11

[7:0]

System clock

The default value of these two registers is 0x0100. Note that Register 0E11 and

respectively. Because the previous register contains a data instruction, these two

registers define a starting address (in this case, 0x0100). The controller stores 0x0100

in the EEPROM and increments the EEPROM pointer by 2. It then transfers nine bytes

from the register map (beginning at Address 0x0100) to the EEPROM and increments

the EEPROM address pointer by 10 (nine data bytes and one checksum byte). The nine

bytes transferred correspond to the system clock parameters in the register map.

0E12

[7:0]

0E13

[7:0]

I/O update

The default value of this register is 0x80, which the controller interprets as an I/O

update instruction. The controller stores 0x80 in the EEPROM and increments the

EEPROM address pointer.

Table 142. EEPROM Storage Sequence for System Clock Calibration

Address

Bits

Bit Name

Description

0E14

[7:0]

SYSCLK calibrate

The default value of this register is 0xA0, which the controller interprets as a calibrate

instruction. The controller stores 0xA0 in the EEPROM and increments the EEPROM

address pointer.

Table 143. EEPROM Storage Sequence for General Configuration Settings

Address

Bits

Bit Name

Description

0E15

[7:0]

General

The default value of this register is 0x14, which the controller interprets as a data

instruction. Its decimal value is 20, which tells the controller to transfer 21 bytes of

data (20 + 1) beginning at the address specified by the next two bytes. The controller

stores 0x14 in the EEPROM and increments the EEPROM address pointer.

0E16

[7:0]

General

The default value of these two registers is 0x0200. Note that Register 0E16 and

address, respectively. Because the previous register contains a data instruction,

these two registers define a starting address (in this case, 0x0200). The controller

stores 0x0200 in the EEPROM and increments the EEPROM pointer by 2. It then

transfers 21 bytes from the register map (beginning at Address 0x0200) to the

EEPROM and increments the EEPROM address pointer by 22 (21 data bytes and one

checksum byte). The 21 bytes transferred correspond to the general configuration

parameters in the register map.

0E17

[7:0]

Table 144. EEPROM Storage Sequence for DPLL Settings

Address

Bits

Bit Name

Description

0E18

[7:0]

DPLL

The default value of this register is 0x1B, which the controller interprets as a data

instruction. Its decimal value is 27, which tells the controller to transfer 28 bytes

of data (27 + 1) beginning at the address specified by the next two bytes. The

controller stores 0x1B in the EEPROM and increments the EEPROM address pointer.

0E19

[7:0]

DPLL

The default value of these two registers is 0x0300. Note that Register 0E19 and

respectively. Because the previous register contains a data instruction, these two

registers define a starting address (in this case, 0x0300). The controller stores 0x0300

in the EEPROM and increments the EEPROM pointer by 2. It then transfers 28 bytes

from the register map (beginning at Address 0x0300) to the EEPROM and increments

the EEPROM address pointer by 29 (28 data bytes and one checksum byte). The

28 bytes transferred correspond to the DPLL parameters in the register map.

0E1A

[7:0]

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