AD9548SLASHPCBZ datasheet(98/112 Pages) AD

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AD9548

Rev. 0 | Page 98 of 112

If not masked via the IRQ mask register (Address 0209 to Address 0210), then the appropriate IRQ monitor bit is set to a Logic 1 when the

indicated event occurs. These bits can only be cleared via the IRQ clearing register (Address 0A04 to Address 0A0B), the reset all IRQs bit

(Register 0A03, Bit 1), or a device reset.

Table 132. IRQ Monitor for SYSCLK

Address

Bits

Bit Name

Description

0D02

[7:6]

Unused

[5]

SYSCLK unlocked

Indicates a SYSCLK PLL state transition from locked to unlocked

[4]

SYSCLK locked

Indicates a SYSCLK PLL state transition from unlocked to locked

[3:2]

Unused

[1]

SYSCLK Cal complete

Indicates that SYSCLK calibration has completed

[0]

SYSCLK Cal started

Indicates that SYSCLK calibration has begun

Table 133. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM

Address

Bits

Bit Name

Description

0D03

[7:4]

Unused

[3]

Distribution sync

Indicates a distribution sync event

[2]

Watchdog timer

Indicates expiration of the watchdog timer

[1]

EEPROM fault

Indicates a fault during an EEPROM load or save operation

[0]

EEPROM complete

Indicates successful completion of an EEPROM load or save operation

Table 134. IRQ Monitor for the Digital PLL

Address

Bits

Bit Name

Description

0D04

[7]

Switching

Indicates that the DPLL is switching to a new reference

[6]

Closed

Indicates that the DPLL has entered closed-loop operation

[5]

Freerun

Indicates that the DPLL has entered free-run mode

[4]

Holdover

Indicates that the DPLL has entered holdover mode

[3]

Freq unlocked

Indicates that the DPLL lost frequency lock

[2]

Freq locked

Indicates that the DPLL has acquired frequency lock

[1]

Phase unlocked

Indicates that the DPLL lost phase lock

[0]

Phase locked

Indicates that the DPLL has acquired phase lock

Table 135. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit

Address

Bits

Bit Name

Description

0D05

[7:5]

Unused

[4]

History updated

Indicates the occurrence of a tuning word history update

[3]

Freq unclamped

Indicates a frequency limiter state transition from clamped to unclamped

[2]

Freq clamped

Indicates a frequency limiter state transition from unclamped to clamped

[1]

Phase slew unlimited

Indicates a phase slew limiter state transition from slew limiting to not slew limiting

[0]

Phase slew limited

Indicates a phase slew limiter state transition from not slew limiting to slew limiting

Table 136. IRQ Monitor for Reference Inputs

Address

Bits

Bit Name

Description

0D06

[7]

Ref AA new profile

Indicates that Ref AA has switched to a new profile

[6]

Ref AA validated

Indicates that Ref AA has been validated

[5]

Ref AA fault cleared

Indicates that Ref AA has been cleared of a previous fault

[4]

Ref AA fault

Indicates that Ref AA has been faulted

[3]

Ref A new profile

Indicates that Ref A has switched to a new profile

[2]

Ref A validated

Indicates that Ref A has been validated

[1]

Ref A fault cleared

Indicates that Ref A has been cleared of a previous fault

[0]

Ref A fault

Indicates that Ref A has been faulted

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