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AD9548/PCBZ датащи(PDF) 92 Page - Analog Devices |
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AD9548/PCBZ датащи(HTML) 92 Page - Analog Devices |
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92 / 112 page ![]() AD9548 Rev. 0 | Page 92 of 112 Table 117. Lock Detectors—Profile 3 Address Bits Bit Name Description 06DB [7:0] Phase lock threshold (in picoseconds) Phase lock threshold, Bits[7:0] 06DC [7:0] Phase lock threshold, Bits[15:8] 06DD [7:0] Phase lock fill rate Phase lock fill rate, Bits[7:0] 06DE [7:0] Phase lock drain rate Phase lock drain rate, Bits[7:0] 06DF [7:0] Frequency lock thresh- old (in picoseconds) Frequency lock threshold, Bits[7:0] 06E0 [7:0] Frequency lock threshold, Bits[15:8] 06E1 [7:0] Frequency lock threshold, Bits[23:16] 06E2 [7:0] Frequency lock fill rate Frequency lock fill rate, Bits[7:0] 06E3 [7:0] Frequency lock drain rate Frequency lock drain rate, Bits[7:0] 06E4 to 06FF [7:0] Unused Register 0700 to Register 07FF—Profile 4 to Profile 7 Profile 4 (Register 0700 to Register 0731) is identical to Profile 0 (Register 0600 to Register0631). Profile 5 (Register 0732 to Register 077F) is identical to Profile 1 (Register 0632 to Register 067F). Profile 6 (Register 0780 to Register 07B1) is identical to Profile 2 (Register 0680 to Register 06B1). Profile 7 (Register 07B2 to Register 07FF) is identical to Profile 3 (Register 06B2 to Register 06FF). OPERATIONAL CONTROLS (REGISTER 0A00 TO REGISTER 0A10) Table 118. General Power-Down Address Bits Bit Name Description 0A00 [7] Reset sans reg map Reset internal hardware but retain programmed register values. 0 (default) = normal operation. 1 = reset. [6] Unused [5] SYSCLK power-down Place SYSCLK input and PLL in deep sleep mode. 0 (default) = normal operation. 1 = power-down. [4] Reference power- down Place reference clock inputs in deep sleep mode. 0 (default) = normal operation. 1 = power-down. [3] TDC power-down Place the time-to-digital converter in deep sleep mode. 0 (default) = normal operation. 1 = power-down. [2] DAC power-down Place the DAC in deep sleep mode. 0 (default) = normal operation. 1 = power-down. [1] Dist power-down Place the clock distribution outputs in deep sleep mode. 0 (default) = normal operation. 1 = power-down. [0] Full power-down Place the entire device in deep sleep mode. 0 (default) = normal operation. 1 = power-down. |
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