AD9548SLASHPCBZ datasheet(17/112 Pages) AD

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AD9548

Rev. 0 | Page 17 of 112

Pin No.

Mnemonic

Input/

Output

Pin Type

Description

SYSCLKP

Differential

input

System Clock Input. SYSCLKP contains internal dc biasing and should be ac-

coupled with a 0.01 μF capacitor, except when using a crystal, in which case

connect the crystal across SYSCLKP and SYSCLKN. Single-ended 1.8 V CMOS is

also an option but can introduce a spur if the duty cycle is not 50%. When using

SYSCLKP as a single-ended input, connect a 0.01 μF capacitor from SYSCLKN to

ground.

56, 75

No Connection. These pins should be left floating.

AVDD

Power

1.8 V Analog Power Supply.

57, 58

TDC_VRB,

TDC_VRT

Use capacitive decoupling on these pins (see Figure 38).

60, 66, 67,

AVDD3

Power

3.3 V Analog (Reference Input) Power Supply.

REFA

Differential

input

Reference A Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.

REFAA

Differential

input

Complementary Reference A Input. Complementary signal to the input provided

on Pin 61. The user can configure this pin as a separate single-ended input.

63, 70, 74

AVDD

Power

1.8 V Analog (Reference Input) Power Supply.

REFB

Differential

input

Reference B Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.

REFBB

Differential

input

Complementary Reference B Input. Complementary signal to the input provided

on Pin 64. The user can configure this pin as a separate single-ended input.

REFC

Differential

input

Reference C Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.

REFCC

Differential

input

Complementary Reference C Input. Complementary signal to the input provided

on Pin 68. The user can configure this pin as a separate single-ended input.

REFD

Differential

input

Reference D Input. This internally biased input is typically ac-coupled and, when

configured as such, can accept any differential signal with single-ended swing up

to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.

REFDD

Differential

input

Complementary Reference D Input. Complementary signal to the input provided

on Pin 71. The user can configure this pin as a separate single-ended input.

IRQ

Logic

Interrupt Request Line.

78, 79, 80,

81, 84, 85,

86, 87

M0, M1, M2,

M3, M4, M5,

M6, M7

I/O

3.3 V CMOS

Configurable I/O Pins. These pins are configured under program control.

VSS

Exposed

pad

The exposed pad must be connected to ground (VSS).

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