AD9548SLASHPCBZ datasheet(70/112 Pages) AD

70 / 112 page

AD9548

Rev. 0 | Page 70 of 112

SERIAL PORT CONFIGURATION (REGISTER 0000 TO REGISTER 0005)

Table 36. Serial Configuration

Address

Bits

Bit Name

Description

0000

[7]

Unidirectional

Select SPI port SDO pin operating mode.

0 (default) = 3-wire.

1 = 4-wire (SDO pin enabled).

[6]

LSB first

Bit order for SPI port.

0 (default) = most significant bit and byte first.

1 = least significant bit and byte first.

[5]

Soft reset

Device reset (invokes an EEPROM download if M[7:3] ≠ 0).

0 (default) = normal operation.

1 = reset.

[4]

Long instruction

16-bit mode (the only mode supported by the device). This bit is read only and reads back as Logic 1.

[0]

Unused

Table 37. Reserved Register

Address

Bits

Bit Name

Description

0001

[7:0]

Unused

Table 38. Silicon Revision Level (Read-Only)

Address

Bits

Bit Name

Description

0002

[7:0]

Reserved

Default = 0x01 = 0b00000001

Table 39. Device ID (Read Only)

Address

Bits

Bit Name

Description

0003

[7:0]

Reserved

Default = 0x48 = 0b01001000

Table 40. Register Readback Control

Address

Bits

Bit Name

Description

0004

[7:1]

Unused

Read buffer register

For buffered registers, serial port readback reads from actual (active) registers instead of

from the buffer.

0 (default) = reads values currently applied to the internal logic of the device.

1 = reads buffered values that take effect on the next assertion of the I/O update.

Table 41. Soft I/O Update

Address

Bits

Bit Name

Description

0005

[7:1]

Unused

I/O update

Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the internal

control registers of the device. This is an autoclearing bit.

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