AD9548SLASHPCBZ datasheet(75/112 Pages) AD

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AD9548

Rev. 0 | Page 75 of 112

DPLL CONFIGURATION (REGISTER 0300 TO REGISTER 031B)

Table 56. Free Running Frequency Tuning Word1

Address

Bits

Bit Name

Description

0300

[7:0]

Frequency

(expressed as a 48-bit

frequency tuning

word)

Free running frequency tuning word, Bits[7:0]

0301

[7:0]

Free running frequency tuning word, Bits[15:8]

0302

[7:0]

Free running frequency tuning word, Bits[23:9]

0303

[7:0]

Free running frequency tuning word, Bits[31:24]

0304

[7:0]

Free running frequency tuning word, Bits[39:32]

0305

[7:0]

Free running frequency tuning word, Bits[47:40]

1 The default free running tuning word is 0x000000 = 0, which equates to 0 Hz.

Table 57. Update TW

Address

Bits

Bit Name

Description

0306

[7:1]

Unused

[0]

Update TW

A Logic 1 written to this bit transfers the free running frequency tuning word (Register

0300 to Register 0305) to the register imbedded in the tuning word processing logic.

Note that it is not necessary to write the update TW bit when the device is in free-run

mode. This is an autoclearing bit.

Table 58. Pull-In Range Lower Limit1

Address

Bits

Bit Name

Description

0307

[7:0]

Pull-in range lower

limit (expressed as a

24-bit frequency

tuning word)

Lower limit pull-in range, Bits[7:0]

0308

[7:0]

Lower limit pull-in range, Bits[15:8]

0309

[7:0]

Lower limit pull-in range, Bits[23:9]

030A

[7:0]

Pull-in range upper

limit (expressed as a

24-bit frequency

tuning word)

Upper limit pull-in range, Bits[7:0]

030B

[7:0]

Upper limit pull-in range, Bits[15:8]

030C

[7:0]

Upper limit pull-in range, Bits[23:9]

1 The default pull-in range lower limit is 0 and the upper range limit is 0xFFFFFF, which effectively spans the full output frequency range of the DDS.

Table 59. DDS Phase Offset1

Address

Bits

Bit Name

Description

030D

[7:0]

Open-loop phase

offset (expressed in

π/215 radians)

DDS phase offset, Bits[7:0]

030E

[7:0]

DDS phase offset, Bits[15:8]

1 The default DDS phase offset is 0.

Table 60. Fixed Closed-Loop Phase Lock Offset1

Address

Bits

Bit Name

Description

030F

[7:0]

Fixed phase lock offset

(expressed in pico-

seconds)

Fixed phase lock offset, Bits[7:0]

0310

[7:0]

Fixed phase lock offset, Bits[15:8]

0311

[7:0]

Fixed phase lock offset, Bits[23:16]

0312

[7:0]

Fixed phase lock offset, Bits[31:24]

0313

[7:0]

Fixed phase lock offset, Bits[39:32]

1 The default fixed closed loop phase lock offset is 0.

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