TMP86CS64AFG datasheet(127/202 Pages) TOSHIBA

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TMP86CS64AFG

11.3.4 Pulse Width Modulation (PWM) Output Mode

The pulse width modulation (PWM) output mode is used to generate the PWM pulse with up to 8 bits of res-

olution by an internal clock.

When a match between the up-counter and the TC4DR value is detected, the logic level output from the

PWM

4 pin becomes low. The up-counter continues counting. When the up-counter overflow occurs, the PWM4

pin becomes high. The INTTC4 interrupt request is generated at this time.

When the timer is stopped, the PWM4 pin is high. Therefore, if the timer is stopped when the PWM4 pin is

low, one PMW cycle may be shorter than the programmed value.

TC4DR is serially connected to the shift register. If TC4DR is programmed during PWM output, the data set

to TC4DR is not shifted until one PWM cycle is completed. Therefore, a pulse can be modulated periodically.

For the first time, the data written to TC4DR is shifted when the timer is started by setting TC4CR<TC4S> to

Note 1: The PWM output mode can be used only in the NORMAL1/2 and IDEL 1/2 modes.

Note 2: In the PWM output mode, program TC4DR immediately after the INTTC4 interrupt request is generated

(typically in the INTTC4 interrupt service routine.) When the programming of TC4DR and the INTTC4 inter-

rupt occur at the same time, an unstable value is shifted, that may result in generation of pulse different

from the programmed value until the next INTTC4 interrupt request is issued.

Figure 11-3 PWM output Mode Timing Chart (TC4)

Internal clock

Shift register

Counter

n + 1

PWM cycle

Match detect

Data shift

Rewrite

Data shift

Match detect

Data shift

Rewrite

PWM4 pin

INTTC4

interrupt request

Timer F/F

TC4DR

TC4CR<TC4S>

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