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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP86CS64AFG датащи(PDF) 72 Page - Toshiba Semiconductor |
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TMP86CS64AFG датащи(HTML) 72 Page - Toshiba Semiconductor |
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72 / 202 page  Page 62 5. I/O Ports TMP86CS64AFG 5.6 Port P5 (P57 to P50) Port P5 is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port P5 input/output control register (P5CR). During reset, the P5CR is initialized to “0”, which configures port P5 as an input mode. The P5 output latches are also initialized to “0”. Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-7 Port P5 Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Read- modify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. P5DR (0005H) 76 543 21 0 P57 P56 P55 P54 P53 P52 P51 P50 (Initial value: 0000 0000) P5CR (000DH) 76 543 21 0 P5CR7 P5CR6 P5CR5 P5CR4 P5CR3 P5CR2 P5CR1 P5CR0 (Initial value: 0000 0000) P5CR I/O control for port P5 (specified for each bit) 0: Input mode 1: Output mode R/W Output latch STOP OUTEN Data input Data output P5CRi P5i D Q |
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