TMP86CS64AFG datasheet(44/202 Pages) TOSHIBA

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Page 34

2. Operational Descriptions

2.2 System Clock Controller

TMP86CS64AFG

(2) Switching from the SLOW1 mode to NORMAL2 mode

Note: After SYSCK is cleared to 0, instructions are executed continuously by the low-frequency clock

during synchronization period for high-frequency and low-frequency clocks.

First, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock. After the warm-up period time required to assure oscillation

stability with the TimerCounter (TC2) has elapsed, clear SYSCR2<SYSCK> to 0 to switch the system clock to the high-frequency

clock. The SLOW mode is also exited by setting the RESET pin to low, which immediately performs normal reset operation. The

NORMAL1 mode is entered after a reset release.

Example :Switching from SLOW1 mode to NORMAL2 mode with TC2

(fc = 16 MHz, warm-up time = 4.0 ms)

SET

(SYSCR2) . 7

: SYSCR2<XEN>¨1

:(starts high-frequency oscillation.)

(TC2CR), 10H

: sets the TC2 mode.

(TC2DRH), 0F8H

: sets the warm-up time.

: (determines the time depending on the frequency and resonator.)

: IMF¨0

SET

(EIRH). 4

: enables INTTC2 interrupt.

: IMF¨1

SET

(TC2CR). 5

: starts TC2.

PINTTC2

CLR

(TC2CR). 5

: stops TC2.

CLR

(SYSCR2). 5

: SYSCR2<SYSCK>¨0

: (switches the system clock to the high-frequency clock.)

RETI

VINTTC2:

PINTTC2

: INTTC2 vector table

High-frequency clock fc

Low-frequency clock fc

Main system clock

SYSCK

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