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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP86CS64AFG датащи(PDF) 68 Page - Toshiba Semiconductor |
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TMP86CS64AFG датащи(HTML) 68 Page - Toshiba Semiconductor |
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68 / 202 page  Page 58 5. I/O Ports TMP86CS64AFG 5.3 Port P2 (P22 to P20) Port P2 is a 3-bit input/output port. During reset, the P2DR is initialized to “1”. It is also used as INT5/STOP1. When used as secondary function pin or an input pin, the output latch should be set to “1”. In the dual-clock mode, the low-frequency oscillator (32.768 kHz) is connected to P21 (XTIN) and P22 (XTOUT) pins. P2 port output latch (P2DR) and P2 port terminal input (P2R) are located on their respective address. When a read instruction is executed for port P2, read data of bits 7 to 3 are unstable. Note: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1, XTEN: bit 6 in SYSCR2 Figure 5-4 Port P2 Note 1: Port P20 is used as STOP1 pin. Therefore, when stop mode is started, however SYSCR1<OUTEN> is set to “1”, port P20 becomes High-Z (input mode). Note 2: Each terminal has a protect diode. Please refer to section “Input/Output Circuitry; (2) Input/Output ports”. P2DR (0002H) 76 543 21 0 P22 XTOUT P21 XTIN P20 INT5 STOP1 (Initial value: **** *111) P2R (002CH) 76 543 21 0 P22IN P21IN P20IN (Initial value: **** ****) Read only Output latch Output latch Output latch Data input (P20IN) Data input (P20) Data output Control input Data input (P21IN) Data input (P21) Data output Data input (P22IN) Data input (P22) Data output STOP OUTEN XTEN fs Osc.enable D Q P20 D Q P21 D Q P22 |
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