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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP86CS64AFG датащи(PDF) 79 Page - Toshiba Semiconductor |
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TMP86CS64AFG датащи(HTML) 79 Page - Toshiba Semiconductor |
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79 / 202 page  Page 69 TMP86CS64AFG 5.11 Port PA (PA7 to PA0) Port PA is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port PA input/output control register (PACR). During reset, the PACR is initialized to “0”, which configures port PA as an input. The PA output latches are also ini- tialized to “0”. Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-12 Port PA Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Read- modify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. Note: However the PAPU is set to “1” (pull-up), the port configured output is not set up pull-up resistor. PADR (0FB6H) 76 543 21 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 (Initial value: 0000 0000) PACR (0FB8H) 76 543 21 0 PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PACR0 (Initial value: 0000 0000) PACR I/O control for port PA (specified for each bit) 0: Input mode 1: Output mode R/W PAPU (0FBAH) 7 6 5 432 10 PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 (Initial value: 0000 0000) PAPU Port PA pull up control register (specified for each bit) 0: Non pull-up 1: Pull-up R/W Output latch STOP OUTEN Data input Data output PACRi PAi VDD D Q Pull-up resistor (Typ. 80 k Ω) PAPUi |
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