TMP86CS64AFG datasheet(70/202 Pages) TOSHIBA

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Page 60

5. I/O Ports

TMP86CS64AFG

5.5 Port P4 (P47 to P40)

Port P4 is an 8-bit input/output port, which can be configured individually as an input or an output under software

control. Input/output mode is specified by the corresponding bit in the port P4 input/output control register (P4CR).

During reset, the P4CR is initialized to “0”, which configures port P4 as an input mode. The P4 output latches are

also initialized to “1”.

It is also used as INT0, INT1, INT2/TC1, TC2, DVO and PPG. When used as secondary function pin, the input pins

(INT0, INT1, INT2, TC1, TC2) should be set to the input mode and the output pins (DVO, PPG) should be set to the

output mode beforehand the output latch should be set to “1”.

Port P4 can be configured individually as a tri-state output or sink open drain output under software control. It is

specified by the corresponding bit in the P4ODE. During reset, the P4ODE is initialized to “0”, and then P4CR is set

to “1”, the tri-state output is configured.

P4 port output latch (P4DR) and P4 port terminal input (P4R) are located on their respective address.

When the input mode and output mode are configured simultaneously, even if the bit manipulate instruction is exe-

cuted, the data of the output latch of the terminal set as the input mode is not influenced of the terminal input.

Port P40, P41, P42, P44, P45, P46 and P47 are also used as SCK2, RXD1, TXD1, RXD2, TXD2, INT3/TC3 and

INT4. When used as secondary function pin, the SCK1 pin should be set to the input or output mode, the input pins

(RXD1, RXD2, INT3/TC3, INT4) should be set to the input mode and the output pins (TXD1, TXD2) should be set

to the output.

Note 1: i = 7 to 0

Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1

Figure 5-6 Port P4

Output latch

STOP

OUTEN

Data input (P4R)

Data output

Data input (P4DR)

Control output

Control input

P4ODEi

P4CRi

P4i

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