TMP86CS64AFG datasheet(26/202 Pages) TOSHIBA

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Page 16

2. Operational Descriptions

2.2 System Clock Controller

TMP86CS64AFG

Note 3: 0 must be written to the bit 7, 6, 4 through 0 of CGCR.

Note 1: Do not set DV7CK to 1 in the single-clock mode.

Note 2: Do not set DV7CK to 1 until the low-frequency clock oscillation is stabilized.

Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care

Note 4: In the SLOW 1/2 or SLEEP1/2 mode, fs is input to the 7th stage of the divider regardless of DV7CK setting.

Note 5: When the STOP mode is entered from the NORMAL1/2 mode, the output of the 6th stage of the divider is input to the 7th

stage of the divider during warm up after exiting from the STOP mode regardless of DV7CK setting.

2.2.2.2 Machine Cycle

The instruction execution and peripheral hardware operation are synchronized with the system clock.

The minimum instruction execution unit is called a "machine cycle". There are 10 types of instructions for

TLCS-870/C Series, which are 1-cycle instructions to be executed within 1-cycle through 10-cycle

instructions to be executed within ten cycles.

A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.

Figure 2-5 Machine Cycle

2.2.3 Operating Modes

The operating mode controller starts and stops the oscillators for the high-frequency and low-frequency

clocks, and switches the main system clock. The device has the single-clock, dual-clock and STOP modes,

which can be controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operat-

ing mode transition.

Timing Generator Control Resister

TBTCR

(0036H)

654

321

(DVOE

(DVOCK)

DV7CK

(TBTE

(TBTCK)

(Initial value: 0000 0000)

DV7CK

Selection of the input clock

to the 7th stage of the divider

0: fc/28[Hz]

1: fs

R/W

Main system

clock

State

Machine cycle

1/fc or 1/fs [s]

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