TMP86CS64AFG datasheet(53/202 Pages) TOSHIBA

53 / 202 page

Page 43

TMP86CS64AFG

3.3 Interrupt Source Selector (INTSEL)

Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the

interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt

requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL reg-

ister must be set appropriately before interrupt requests are generated.

The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL.

1. INTTBT and INT2 share the interrupt source level whose priority is 9.

2. INTTC1 and INT3 share the interrupt source level whose priority is 10.

3. INTSIO1 and INT4 share the interrupt source level whose priority is 14.

4. INTTRX and INT5 share the interrupt source level whose priority is 15.

5. INTADC and INTSIO2 share the interrupt source level whose priority is 16.

3.4 Interrupt Sequence

An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to

“0” by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2

µs @16 MHz) after the

completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return

instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing

chart of interrupt acceptance processing.

3.4.1 Interrupt acceptance processing is packaged as follows.

a. The interrupt master enable flag (IMF) is cleared to “0” in order to disable the acceptance of any fol-

lowing interrupt.

b. The interrupt latch (IL) for the interrupt source accepted is cleared to “0”.

c. The contents of the program counter (PC) and the program status word, including the interrupt master

enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Mean-

while, the stack pointer (SP) is decremented by 3.

d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vec-

tor table, is transferred to the program counter.

e. The instruction stored at the entry address of the interrupt service program is executed.

Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved.

Interrupt source selector

INTSEL

(003EH)

76543

210

IL8ER

IL9ER

IL13ER

IL14ER

IL15ER

(Initial value: 00** *000)

IL8ER

Selects INTTBT or INT2

0: INTTBT

1: INT2

R/W

IL9ER

Selects INTTC1 or INT3

0: INTTC1

1: INT3

R/W

IL13ER

Selects INTSIO1 or INT4

0: INTSIO1

1: INT4

R/W

IL14ER

Selects INTTRX or INT5

0: INTTRX

1: INT5

R/W

IL15ER

Selects INTADC or INTSIO2

0: INTADC

1: INTSIO2

R/W

TMP86CS64AFG датащи(PDF) 53 Page - Toshiba Semiconductor

TMP86CS64AFG датащи(HTML) 53 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL