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TMP86CS64AFG датащи(PDF) 40 Page - Toshiba Semiconductor |
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TMP86CS64AFG датащи(HTML) 40 Page - Toshiba Semiconductor |
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40 / 202 page ![]() Page 30 2. Operational Descriptions 2.2 System Clock Controller TMP86CS64AFG 2.2.4.3 IDLE0 and SLEEP0 Modes The IDLE0 mode is controlled by the system control register 2 (SYSCR2) and time base timer. The fol- lowing status is held during the IDLE0 mode. • The timing generator stops the clock distribution to the on-chip peripherals except the time base timer. • The data memory, registers, program status words and port output latches hold the status that acti- vated the IDLE0 or SLEEP0 mode. • The program counter holds the address of the instruction after next to the instruction to activate the IDLE0 or SLEEP0 mode. Note: Before entering the IDLE0 or SLEEP0 mode, the on-chip peripherals must be disabled. Figure 2-12 IDLE0 or SLEEP0 Mode Stopping operations of the on-chip functions (Instruction) CPU and WDT halted Interrupt processing Reset Yes No No No "0" Reset input Yes Yes (Interrupt service routine) (Normal execution) TBTCR<TBTEN> TBT interrupt enabled Falling the TBT source clock IMF = "1" Yes "1" No No Entering the IDLE0 or SLEEP0 mode (Instruction) Execution of the instruction immediately following the instruction that activated the IDLE0 or SLEEP0 mode |
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