TMP86CS64AFG datasheet(89/202 Pages) TOSHIBA

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Page 79

TMP86CS64AFG

7. Time Base Timer (TBT)

The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base

timer interrupt (INTTBT).

7.1 Time Base Timer

7.1.1 Configuration

Figure 7-1 Time Base Timer configuration

7.1.2 Control

Time Base Timer is controled by Time Base Timer control register (TBTCR).

Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care

Time Base Timer Control Register

TBTCR

(0036H)

(DVOEN)

(DVOCK)

(DV7CK)

TBTEN

TBTCK

(Initial Value: 0000 0000)

TBTEN

Time Base Timer

Enable / Disable

0: Disable

1: Enable

TBTCK

Time Base Timer interrupt

Frequency select : [Hz]

NORMAL1/2, IDLE1/2 Mode

SLOW1/2

SLEEP1/2

Mode

R/W

DV7CK = 0

DV7CK = 1

DV1CK=0

DV1CK=1

DV1CK=0

DV1CK=1

000

fc/223

fc/224

fs/215

001

fc/221

fc/222

fs/213

010

fc/216

fc/217

fs/28

–

011

fc/214

fc/215

fs/26

–

100

fc/213

fc/214

fs/25

–

101

fc/212

fc/213

fs/24

–

110

fc/211

fc/212

fs/23

–

111

fc/29

fc/210

fs/2

–

fc/223,fc/224 or fs/215

fc/221,fc/222 or fs/213

fc/216,fc/217 or fs/28

fc/214,fc/215 or fs/26

fc/213,fc/214 or fs/25

fc/212,fc/213 or fs/24

fc/211,fc/212 or fs/23

fc/29,fc/210 or fs/2

TBTCR

TBTEN

TBTCK

MPX

Source clock

Falling edge

detector

Time base timer control register

INTTBT

interrupt request

IDLE0, SLEEP0

release request

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