TMP86CS64AFG datasheet(90/202 Pages) TOSHIBA

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Page 80

7. Time Base Timer (TBT)

7.1 Time Base Timer

TMP86CS64AFG

Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt fre-

quency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be per-

formed simultaneously.

7.1.3 Function

An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider

output of the timing generato which is selected by TBTCK. ) after time base timer has been enabled.

The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set

interrupt period ( Figure 7-2 ).

Figure 7-2 Time Base Timer Interrupt

Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt.

(TBTCR) , 00000010B

; TBTCK

← 010

(TBTCR) , 00001010B

; TBTEN

← 1

; IMF

← 0

SET

(EIRH) . 0

Table 7-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz )

TBTCK

Time Base Timer Interrupt Frequency [Hz]

NORMAL1/2, IDLE1/2 Mode

SLOW1/2, SLEEP1/2 Mode

DV7CK = 0

DV7CK = 1

DV1CK = 0

DV1CK = 1

DV1CK = 0

DV1CK = 1

000

1.91

0.95

001

7.63

3.81

010

244.14

122.07

128

–

011

976.56

488.28

512

–

100

1953.13

976.56

1024

–

101

3906.25

1953.13

2048

–

110

7812.5

3906.25

4096

–

111

31250

15625

16384

–

Source clock

Enable TBT

Interrupt period

TBTCR<TBTEN>

INTTBT

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