TMP86CS64AFG datasheet(24/202 Pages) TOSHIBA

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Page 14

2. Operational Descriptions

2.2 System Clock Controller

TMP86CS64AFG

2.2.2 Timing Generator

The timing generator generates various types of system clocks which are supplied to the CPU core or periph-

eral hardware from the basic clock (fc or fs). The timing generator provides the following functions.

1. Generating the main system clock

2. Generating the divider output (DVO) pulses

3. Generating the source clocks for the time base timer

4. Generating the source clocks for the watchdog timer

5. Generating the internal source clocks for the TimerCounter

6. Generating the warm-up clocks upon exit from the STOP mode

2.2.2.1 Timing Generator Configuration

The timing generator consists of a 3-stage prescaler, a 21-stage divider, a main system clock generator

and a machine cycle counter.

Either the clock fc/4 output from the 2nd stage or the clock fc/8 output from the 3rd stage can be

selected as the clock input to the 1st stage of the divider by CGCR<DV1CK>. This function enables to

operate the peripheral circuits without program change by inputting fc/8 to the 1st stage of the divider

when the operation clock is multiplied by 2. (ex., 8 MHz to 16 MHz)

The input clock to the 7th stage of the divider depends on SYSCR2<SYSCK>, TBTCR<DV7CK> and

CGCR<DV1CK> settings, as shown in Table 2-2.

The prescaler and divider are cleared to 0 upon reset and entry to/exit from the STOP mode.

Note: TBTCR<DV7CK> indicates the bit 4 (DV7CK) of the timing generator (TBTCR). Hereafter, this nota-

tional convention is used for each functional bit of the register.

Note 1: Do not set TBTCR<DV7CK> to 1 during the NORMAL1 or IDLE1 mode.

Note 2: Since the input clock to the 1st stage of the divider is stopped in the SLOW1/2 or SLEEP1/2 mode,

output from the 1st to 7th stages of the divider is also stopped.

Table 2-1 Divider Output

Divider Output

DV1CK = 0

DV1CK = 1

DV1G

DV2G

DV3G

DV4

DV5

DV1G

DV2G

DV3G

DV4

DV5

fc/23

fc/24

fc/25

fc/26

fc/27

fc/24

fc/25

fc/26

fc/27

fc/28

Table 2-2 Input Clock to 7th Stage of the Divider [Hz]

NORMAL1, IDLE1 mode

NORMAL2, IDLE2 mode (SYSCK=0)

SLOW1/2, SLEEP1/2

mode

(SYSCK = 1)

DV7CK = 0

DV7CK = 1

DV1CK = 0

DV1CK = 1

DV1CK = 0

DV1CK = 1

fc/28

fc/29

fc/28

fc/29

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