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TMP86CS64AFG датащи(PDF) 67 Page - Toshiba Semiconductor |
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TMP86CS64AFG датащи(HTML) 67 Page - Toshiba Semiconductor |
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67 / 202 page ![]() Page 57 TMP86CS64AFG 5.2 Port P1 (P17 to P10) Port P1 is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port P1 input/output control register (P1CR). During reset, the P1CR is initialized to “0”, which configures port P1 as an input mode. The P1 output latches are also initialized to “0”. It is also used as INT0, INT1, INT2/TC1, TC2, DVO and PPG. When used as secondary function pin, the input pins (INT0, INT1, INT2, TC1,TC2) should be set to the input mode and the output pins (DVO, PPG) should be set to the output mode beforehand the output latch should be set to “1”. Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-3 Port P1 Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Read- modify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. P1DR (0001H) 76 543 21 0 P17 P16 P15 TC2 P14 PPG P13 DVO P12 INT2 TC1 P11 INT1 P10 INT0 (Initial value: 0000 0000) P1CR (0009H) 76 543 21 0 P1CR7 P1CR6 P1CR5 P1CR4 P1CR3 P1CR2 P1CR1 P1CR0 (Initial value: 0000 0000) P1CR I/O control for port P1 (specified for each bit) 0: Input mode 1: Output mode R/W Output latch STOP OUTEN Data input Data output P1CRi P1i D Q Control output Control input |
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