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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP86CS64AFG датащи(PDF) 80 Page - Toshiba Semiconductor |
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TMP86CS64AFG датащи(HTML) 80 Page - Toshiba Semiconductor |
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80 / 202 page  Page 70 5. I/O Ports TMP86CS64AFG 5.12 Port PB (PB7 to PB0) Port PB is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port PB input/output control register (PBCR). During reset, the PBCR is initialized to “0” which configures port PB as an input. The PB output latches are also ini- tialized to “0”. Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-13 Port PB and PBCR Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Read- modify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. Note: However the PBPU is set to “1” (pull-up), the port configured output is not set up pull-up resistor. PBDR (0FB7H) 76 543 21 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 (Initial value: 0000 0000) PBCR (0FB9H) 76 543 21 0 PBCR7 PBCR6 PBCR5 PBCR4 PBCR3 PBCR2 PBCR1 PBCR0 (Initial value: 0000 0000) PBCR I/O control for port PB (specified for each bit) 0: Input mode 1: Output mode R/W PBPU (0FBBH) 7 6 5 432 10 PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 (Initial value: 0000 0000) PBPU Port PB pull up control register (specified for each bit) 0: Non pull-up 1: Pull-up R/W Output latch STOP OUTEN Data input Data output PBCRi PBi VDD D Q Pull-up resistor (Typ. 80 k Ω) PBPUi |
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