TMP86CS64AFG datasheet(65/202 Pages) TOSHIBA

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Page 55

TMP86CS64AFG

5. I/O Ports

The TMP86CS64AFG have 12 parallel input/output ports (91 pins) as follows.

1. Port P0 (8-bit I/O port)

2. Port P1 (8-bit I/O port)

• External interrupt input, timer/counter input, divider output.

3. Port P2 (3-bit I/O port)

• External interrupt input, STOP mode release signal input.

4. Port P3 (8-bit I/O port)

• Timer/counter input, serial interface input/output.

5. Port P4 (8-bit I/O port)

• Timer/counter input, serial interface input/output, external interrupt input.

6. Port P5 (8-bit I/O port)

7. Port P6 (8-bit I/O port)

• Analog input.

8. Port P7 (8-bit I/O port)

• Analog input, STOP mode release signal input.

9. Port P8 (8-bit I/O port)

10. Port P9 (8-bit I/O port)

11. Port PA (8-bit I/O port)

12. Port PB (8-bit I/O port)

Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external

input data should be externally held until the input data is read from outside or reading should be performed several

timer before processing. Figure 5-1 shows input/output timing examples.

External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This

timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro-

gram.

Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O

port.

Note: The positions of the read and write cycles may vary, depending on the instruction.

Figure 5-1 Input/Output Timing (Example)

Instruction

execution cycle

Input strobe

Data input

Ex: LD A, (x)

Fetch cycle

Read cycle

S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3

Instruction

execution cycle

Output strobe

Data output

Ex: LD (x), A

Fetch cycle

Write cycle

S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3

(a) Input timing

(b) Output timing

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