TMP86CS64AFG datasheet(125/202 Pages) TOSHIBA

номер детали	TMP86CS64AFG

подробное описание детали	8 Bit Microcontroller

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Page 115

TMP86CS64AFG

11.3.2 Event Counter Mode

In the event counter mode, the up-counter counts up at the rising edge of the input pulse to the TC4 pin.

When a match between the up-counter and the TC4DR value is detected, an INTTC4 interrupt is generated

and the up-counter is cleared. After being cleared, the up-counter restarts counting at rising edge of the TC4

pin. Since a match is detected at the falling edge of the input pulse to the TC4 pin, the INTTC4 interrupt

request is generated at the falling edge immediately after the up-counter reaches the value set in TC4DR.

The minimum pulse width applied to the TC4 pin are shown in Table 11-2. The pulse width larger than two

machine cycles is required for high- and low-going pulses.

Note:The event counter mode can not used in the SLOW1/2 and SLEEP1/2 modes since the external clock is not

supplied in these modes.

Table 11-2 External Source Clock for TimerCounter 4

Minimum Pulse Width

NORMAL1/2, IDLE1/2 mode

High-going

23/fc

Low-going

23/fc

TMP86CS64AFG датащи(PDF) 125 Page - Toshiba Semiconductor