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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMP86CS64AFG датащи(PDF) 66 Page - Toshiba Semiconductor |
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TMP86CS64AFG датащи(HTML) 66 Page - Toshiba Semiconductor |
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66 / 202 page  Page 56 5. I/O Ports TMP86CS64AFG 5.1 Port P0 (P07 to P00) Port P0 is an 8-bit input/output port, which can be configured individually as an input or an output under software control. Input/output mode is specified by the corresponding bit in the port P0 input/output control register (P0CR). During reset, the P0CR is initialized to “0”, which configures port P0 as an input. The P0 output latches are also ini- tialized to “0”. Note 1: i = 7 to 0 Note 2: STOP: bit 7 in SYSCR1, OUTEN: bit 4 in SYSCR1 Figure 5-2 Port P0 Note: When used as an input mode, read-modify-write instructions such as bit manipulate instructions cannot be used. Read- modify-write instruction writes the all data of 8-bit after read and modified. Because a bit setting input mode reads data of terminal, the output latch is changed by these instructions. P0DR (0000H) 76 543 21 0 P07 P06 P05 P04 P03 P02 P01 P00 (Initial value: 0000 0000) P0CR (0008H) 76 543 21 0 P0CR7 P0CR6 P0CR5 P0CR4 P0CR3 P0CR2 P0CR1 P0CR0 (Initial value: 0000 0000) P0CR I/O control for port P0 (specified for each bit) 0: Input mode 1: Output mode R/W Output latch STOP OUTEN Data input Data output P0CRi P0i D Q |
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