TMP86CS64AFG datasheet(130/202 Pages) TOSHIBA

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Page 120

12. 8-Bit TimerCounter 5 (TC5)

12.1 Configuration

TMP86CS64AFG

12.2 TimerCounter Control

The TimerCounter 5 is controlled by the TimerCounter 5 control register (TC5CR) and timer registers 5 (TC5DR).

Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care

Note 2: To set the timer registers, the following relationship must be satisfied.

≤ TC5DR ≤ 255

Note 3: To start timer operation (TC5S = 0

→ 1) or disable timer operation (TC5S = 1→ 0), do not change the

TC5CR<TC5M, TC5CK> setting. During timer operation (TC5S = 1

→ 1), do not change it, either. If the setting is

programmed during timer operation, counting is not performed correctly.

Note 4: The event counter and PWM output modes are used only in the NOMAL1/2 and IDLE1/2 modes.

Note 5: When the STOP mode is entered, the start control (TC5S) is cleared to “0” automatically.

Note 6: The bit 6 and 7 of TC5CR are read as a don’t care when these bits are read.

Note 7: In the timer, event counter and PDO modes, do not change the TC5DR setting when the timer is running.

Note 8: When the high-frequency clock fc exceeds 10 MHz, do not select the source clock of TC5CK = 110.

Note 9: The operating clock fs can not be used in NORMAL1 or IDEL1 mode (when low-frequency oscillation is stopped.)

Note 10:For available source clocks depending on the operation mode, refer to the following table.

Timer Register and Control Register

TC5DR

(0019)

543

Read/Write (Initial value: 1111 1111)

TC5CR

(0015)

543

TC5S

TC5CK

TC5M

Read/Write (Initial value: **00 0000)

TC5S

TC5 start control

0: Stop and counter clear

1: Start

R/W

TC5CK

TC5 source clock select

[Hz]

NORMAL1/2, IDLE1/2 mode

Divider

SLOW1/2,

SLEEP1/2

mode

R/W

DV7CK

= 0DV7CK = 1

DV1CK

= 0DV1CK = 1DV1CK = 0DV1CK = 1

000

fc/211

fc/212

fs/23

DV9

fs/23

001

fc/27

fc/28

fc/27

fc/28

DV5

–

010

fc/25

fc/26

fc/25

fc/26

DV3

–

011

fc/23

fc/24

fc/23

fc/24

DV1

–

100

fc/22

fc/23

fc/22

fc/23

––

101

fc/2

fc/22

fc/2

fc/22

––

110

fc/2

–

111

External clock (TC5 pin input)

TC5M

TC5 operating mode

select

00: Timer/event counter mode

01: Reserved

10: Programmable divider output (PDO) mode

11: Pulse width modulation (PWM) output mode

R/W

TC5CK

Timer Mode

Event Counter Mode

PDO Mode

PWM Mode

000

−

001

−

010

−

011

−−

100

−

−−

101

−−−

110

−−

−

111

−

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