TMPR4955AF datasheet(135/168 Pages) TOSHIBA

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Chapter 7 JTAG Interface

7-1

Chapter 7.

JTAG Interface

The TX4955A processor provides a boundary-scan interface that is compatible with Joint Test

Action Group (JTAG) specifications, using the industry-standard JTAG protocol (IEEE Standard

1149.1/D6).

This chapter describes that interface, including descriptions of boundary scanning, the pins and

signals used by the interface, and the Test Access Port (TAP).

7.1

What Boundary Scanning Is

With the evolution of ever-denser integrated circuits (ICs), surface-mounted devices,

double-sided component mounting on printed-circuit boards (PCBs), and buried vias, in-circuit

tests that depend upon making physical contact with internal board and chip connections have

become more and more difficult to use. The greater complexity of ICs has also meant that tests

to fully exercise these chips have become much larger and more difficult to write.

One solution to this difficulty has been the development of

boundary-scan circuits. A

boundary-scan circuit is a series of shift register cells placed between each pin and the internal

circuitry of the IC to which the pin is connected, as shown in Figure 7.1.1. Normally, these

boundary-scan cells are bypassed; when the IC enters test mode, however, the scan cells can be

directed by the test program to pass data along the shift register path and perform various

diagnostic tests. To accomplish this, the tests use the four signals described in the next section:

JTDI

JTDI, JTDO

JTDO

JTDO, JTMS

JTMS

JTMS, JTCK

JTCK

JTCK, and TRST

, and TRST

, and TRST*.

Figure 7.1.1 JTAG Boundary-scan Cells

Integrated Circuit

C package pin

Boundary-scan cells

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